From 60c1e279d6ba47262109cab68355cfdbf4d51f80 Mon Sep 17 00:00:00 2001 From: Commander1024 Date: Sun, 20 Sep 2026 23:14:01 +0200 Subject: [PATCH] Add KiCad module carrier PCB draft MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce an editable KiCad 10 schematic and routed two-layer 82 × 80 mm layout with local provisional footprints, validation tooling, and component research. Keep the RS-232 male-module mapping and mechanical clearances explicitly provisional pending hardware verification. --- hardware/PCB/.gitignore | 7 + hardware/PCB/Carrier.kicad_sym | 116 + .../HW678_2x22_Provisional.kicad_mod | 56 + .../MAX3243_Reference_Provisional.kicad_mod | 34 + .../OLED_26mm_I2C_Provisional.kicad_mod | 21 + hardware/PCB/README.md | 261 + hardware/PCB/adafruit-research.md | 142 + hardware/PCB/bom-draft.csv | 8 + hardware/PCB/button-notes.md | 107 + hardware/PCB/footprint-notes.md | 105 + hardware/PCB/fp-lib-table | 6 + hardware/PCB/generate_pcb_draft.py | 221 + hardware/PCB/generate_schematic.py | 167 + hardware/PCB/oled-fit-check.svg | 37 + hardware/PCB/pcb-draft-notes.md | 173 + hardware/PCB/pcb-placement-draft.pdf | Bin 0 -> 50997 bytes ...232 Full Pinout Level-Shifter Breakout.brd | 15545 ++++ ...232 Full Pinout Level-Shifter Breakout.sch | 2696 + hardware/PCB/reference/README.md | 32 + .../PCB/reference/button-omron-b3f-page4.png | Bin 0 -> 348075 bytes hardware/PCB/reference/button-omron-b3f.pdf | Bin 0 -> 711882 bytes hardware/PCB/reference/button-omron-b3f.txt | 753 + hardware/PCB/reference/license.txt | 359 + hardware/PCB/route_pcb_draft.py | 365 + hardware/PCB/rs232-footprint-notes.md | 117 + hardware/PCB/serial-carrier.kicad_pcb | 7954 ++ hardware/PCB/serial-carrier.kicad_pro | 352 + hardware/PCB/serial-carrier.kicad_sch | 400 + hardware/PCB/serial-carrier.pdf | Bin 0 -> 140654 bytes hardware/PCB/sym-lib-table | 3 + hardware/PCB/validate_footprints.py | 129 + hardware/PCB/validate_pcb_draft.py | 94 + hardware/PCB/validate_schematic.py | 94 + hardware/PCB/validation/erc.json | 36 + hardware/PCB/validation/expected-nets.json | 232 + hardware/PCB/validation/pcb-draft-3d.png | Bin 0 -> 97814 bytes hardware/PCB/validation/pcb-draft.png | Bin 0 -> 258145 bytes hardware/PCB/validation/pcb-draft.svg | 8626 ++ hardware/PCB/validation/pcb-parity-drc.json | 53 + .../PCB/validation/pcb-routing-all-drc.json | 37 + .../PCB/validation/pcb-routing-baseline.json | 911 + .../PCB/validation/pcb-routing-check.json | 85 + hardware/PCB/validation/pcb-routing-check.py | 122 + hardware/PCB/validation/pcb-routing-drc.json | 37 + .../PCB/validation/pcb-routing-dry-run.log | 58 + .../validation/pcb-routing-input.kicad_pcb | 3022 + .../PCB/validation/pcb-routing-pass1-drc.json | 244 + .../PCB/validation/pcb-routing-pass2-drc.json | 221 + hardware/PCB/validation/pcb-routing-pass2.log | 70 + hardware/PCB/validation/pcb-routing-pass3.log | 70 + hardware/PCB/validation/pcb-routing-run.json | 665 + .../PCB/validation/pcb-routing-summary.md | 139 + .../PCB/validation/pcb-source-netlist.xml | 604 + .../validation/pcb-validation-summary.json | 47 + hardware/PCB/validation/schematic-preview.png | Bin 0 -> 130181 bytes hardware/PCB/validation/serial-carrier.svg | 77687 ++++++++++++++++ hardware/PCB/validation/serial-carrier.xml | 604 + hardware/PCB/validation/summary.txt | 8 + 58 files changed, 123932 insertions(+) create mode 100644 hardware/PCB/.gitignore create mode 100644 hardware/PCB/Carrier.kicad_sym create mode 100644 hardware/PCB/Carrier.pretty/HW678_2x22_Provisional.kicad_mod create mode 100644 hardware/PCB/Carrier.pretty/MAX3243_Reference_Provisional.kicad_mod create mode 100644 hardware/PCB/Carrier.pretty/OLED_26mm_I2C_Provisional.kicad_mod create mode 100644 hardware/PCB/README.md create mode 100644 hardware/PCB/adafruit-research.md create mode 100644 hardware/PCB/bom-draft.csv create mode 100644 hardware/PCB/button-notes.md create mode 100644 hardware/PCB/footprint-notes.md create mode 100644 hardware/PCB/fp-lib-table create mode 100644 hardware/PCB/generate_pcb_draft.py create mode 100644 hardware/PCB/generate_schematic.py create mode 100644 hardware/PCB/oled-fit-check.svg create mode 100644 hardware/PCB/pcb-draft-notes.md create mode 100644 hardware/PCB/pcb-placement-draft.pdf create mode 100644 hardware/PCB/reference/Adafruit RS-232 Full Pinout Level-Shifter Breakout.brd create mode 100644 hardware/PCB/reference/Adafruit RS-232 Full Pinout Level-Shifter Breakout.sch create mode 100644 hardware/PCB/reference/README.md create mode 100644 hardware/PCB/reference/button-omron-b3f-page4.png create mode 100644 hardware/PCB/reference/button-omron-b3f.pdf create mode 100644 hardware/PCB/reference/button-omron-b3f.txt create mode 100644 hardware/PCB/reference/license.txt create mode 100644 hardware/PCB/route_pcb_draft.py create mode 100644 hardware/PCB/rs232-footprint-notes.md create mode 100644 hardware/PCB/serial-carrier.kicad_pcb create mode 100644 hardware/PCB/serial-carrier.kicad_pro create mode 100644 hardware/PCB/serial-carrier.kicad_sch create mode 100644 hardware/PCB/serial-carrier.pdf create mode 100644 hardware/PCB/sym-lib-table create mode 100644 hardware/PCB/validate_footprints.py create mode 100644 hardware/PCB/validate_pcb_draft.py create mode 100644 hardware/PCB/validate_schematic.py create mode 100644 hardware/PCB/validation/erc.json create mode 100644 hardware/PCB/validation/expected-nets.json create mode 100644 hardware/PCB/validation/pcb-draft-3d.png create mode 100644 hardware/PCB/validation/pcb-draft.png create mode 100644 hardware/PCB/validation/pcb-draft.svg create mode 100644 hardware/PCB/validation/pcb-parity-drc.json create mode 100644 hardware/PCB/validation/pcb-routing-all-drc.json create mode 100644 hardware/PCB/validation/pcb-routing-baseline.json create mode 100644 hardware/PCB/validation/pcb-routing-check.json create mode 100644 hardware/PCB/validation/pcb-routing-check.py create mode 100644 hardware/PCB/validation/pcb-routing-drc.json create mode 100644 hardware/PCB/validation/pcb-routing-dry-run.log create mode 100644 hardware/PCB/validation/pcb-routing-input.kicad_pcb create mode 100644 hardware/PCB/validation/pcb-routing-pass1-drc.json create mode 100644 hardware/PCB/validation/pcb-routing-pass2-drc.json create mode 100644 hardware/PCB/validation/pcb-routing-pass2.log create mode 100644 hardware/PCB/validation/pcb-routing-pass3.log create mode 100644 hardware/PCB/validation/pcb-routing-run.json create mode 100644 hardware/PCB/validation/pcb-routing-summary.md create mode 100644 hardware/PCB/validation/pcb-source-netlist.xml create mode 100644 hardware/PCB/validation/pcb-validation-summary.json create mode 100644 hardware/PCB/validation/schematic-preview.png create mode 100644 hardware/PCB/validation/serial-carrier.svg create mode 100644 hardware/PCB/validation/serial-carrier.xml create mode 100644 hardware/PCB/validation/summary.txt diff --git a/hardware/PCB/.gitignore b/hardware/PCB/.gitignore new file mode 100644 index 0000000..a0acfff --- /dev/null +++ b/hardware/PCB/.gitignore @@ -0,0 +1,7 @@ +# KiCad per-user state, locks and automatic backups +*.kicad_prl +*.lck +~*.lck +*-backups/ +*.bak +__pycache__/ diff --git a/hardware/PCB/Carrier.kicad_sym b/hardware/PCB/Carrier.kicad_sym new file mode 100644 index 0000000..43945cf --- /dev/null +++ b/hardware/PCB/Carrier.kicad_sym @@ -0,0 +1,116 @@ +(kicad_symbol_lib (version 20231120) (generator "kicad_symbol_editor") +(symbol "HW678_N16R8" (pin_names (offset 0.762)) (in_bom yes) (on_board yes) +(property "Reference" "U" (at 0 34.29 0) (effects (font (size 1.27 1.27)) )) +(property "Value" "HW678_N16R8" (at 0 31.75 0) (effects (font (size 1.27 1.27)) )) +(property "Footprint" "Carrier:HW678_2x22_Provisional" (at 0 0 0) (effects (font (size 1.27 1.27)) (hide yes))) +(property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) (hide yes))) +(property "Description" "HW-678 V0.0.0 / N16R8 carrier interface; project numbering; onboard USB/regulator retained" (at 0 0 0) (effects (font (size 1.27 1.27)) (hide yes))) +(symbol "HW678_N16R8_0_1" (rectangle (start -17.78 29.21) (end 17.78 -29.21) (stroke (width 0.254) (type default)) (fill (type background)))) +(symbol "HW678_N16R8_1_1" +(pin power_out line (at -22.86 26.67 0) (length 5.08) (name "3V3" (effects (font (size 1.016 1.016)) )) (number "1" (effects (font (size 1.016 1.016)) ))) +(pin passive line (at -22.86 24.13 0) (length 5.08) (name "3V3" (effects (font (size 1.016 1.016)) )) (number "2" (effects (font (size 1.016 1.016)) ))) +(pin input line (at -22.86 21.59 0) (length 5.08) (name "EN" (effects (font (size 1.016 1.016)) )) (number "3" (effects (font (size 1.016 1.016)) ))) +(pin input line (at -22.86 19.05 0) (length 5.08) (name "GPIO4" (effects (font (size 1.016 1.016)) )) (number "4" (effects (font (size 1.016 1.016)) ))) +(pin input line (at -22.86 16.51 0) (length 5.08) (name "GPIO5" (effects (font (size 1.016 1.016)) )) (number "5" (effects (font (size 1.016 1.016)) ))) +(pin input line (at -22.86 13.97 0) (length 5.08) (name "GPIO6" (effects (font (size 1.016 1.016)) )) (number "6" (effects (font (size 1.016 1.016)) ))) +(pin output line (at -22.86 11.43 0) (length 5.08) (name "GPIO7" (effects (font (size 1.016 1.016)) )) (number "7" (effects (font (size 1.016 1.016)) ))) +(pin output line (at -22.86 8.89 0) (length 5.08) (name "GPIO15" (effects (font (size 1.016 1.016)) )) (number "8" (effects (font (size 1.016 1.016)) ))) +(pin input line (at -22.86 6.35 0) (length 5.08) (name "GPIO16" (effects (font (size 1.016 1.016)) )) (number "9" (effects (font (size 1.016 1.016)) ))) +(pin output line (at -22.86 3.81 0) (length 5.08) (name "GPIO17" (effects (font (size 1.016 1.016)) )) (number "10" (effects (font (size 1.016 1.016)) ))) +(pin input line (at -22.86 1.27 0) (length 5.08) (name "GPIO18" (effects (font (size 1.016 1.016)) )) (number "11" (effects (font (size 1.016 1.016)) ))) +(pin input line (at -22.86 -1.27 0) (length 5.08) (name "GPIO8" (effects (font (size 1.016 1.016)) )) (number "12" (effects (font (size 1.016 1.016)) ))) +(pin bidirectional line (at -22.86 -3.81 0) (length 5.08) (name "GPIO3" (effects (font (size 1.016 1.016)) )) (number "13" (effects (font (size 1.016 1.016)) ))) +(pin bidirectional line (at -22.86 -6.35 0) (length 5.08) (name "GPIO46" (effects (font (size 1.016 1.016)) )) (number "14" (effects (font (size 1.016 1.016)) ))) +(pin bidirectional line (at -22.86 -8.89 0) (length 5.08) (name "GPIO9" (effects (font (size 1.016 1.016)) )) (number "15" (effects (font (size 1.016 1.016)) ))) +(pin input line (at -22.86 -11.43 0) (length 5.08) (name "GPIO10" (effects (font (size 1.016 1.016)) )) (number "16" (effects (font (size 1.016 1.016)) ))) +(pin bidirectional line (at -22.86 -13.97 0) (length 5.08) (name "GPIO11" (effects (font (size 1.016 1.016)) )) (number "17" (effects (font (size 1.016 1.016)) ))) +(pin output line (at -22.86 -16.51 0) (length 5.08) (name "GPIO12" (effects (font (size 1.016 1.016)) )) (number "18" (effects (font (size 1.016 1.016)) ))) +(pin input line (at -22.86 -19.05 0) (length 5.08) (name "GPIO13" (effects (font (size 1.016 1.016)) )) (number "19" (effects (font (size 1.016 1.016)) ))) +(pin input line (at -22.86 -21.59 0) (length 5.08) (name "GPIO14" (effects (font (size 1.016 1.016)) )) (number "20" (effects (font (size 1.016 1.016)) ))) +(pin passive line (at -22.86 -24.13 0) (length 5.08) (name "5V" (effects (font (size 1.016 1.016)) )) (number "21" (effects (font (size 1.016 1.016)) ))) +(pin power_out line (at -22.86 -26.67 0) (length 5.08) (name "GND" (effects (font (size 1.016 1.016)) )) (number "22" (effects (font (size 1.016 1.016)) ))) +(pin passive line (at 22.86 26.67 180) (length 5.08) (name "GND" (effects (font (size 1.016 1.016)) )) (number "23" (effects (font (size 1.016 1.016)) ))) +(pin bidirectional line (at 22.86 24.13 180) (length 5.08) (name "GPIO43" (effects (font (size 1.016 1.016)) )) (number "24" (effects (font (size 1.016 1.016)) ))) +(pin bidirectional line (at 22.86 21.59 180) (length 5.08) (name "GPIO44" (effects (font (size 1.016 1.016)) )) (number "25" (effects (font (size 1.016 1.016)) ))) +(pin bidirectional line (at 22.86 19.05 180) (length 5.08) (name "GPIO1" (effects (font (size 1.016 1.016)) )) (number "26" (effects (font (size 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+(property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) (hide yes))) +(property "Description" "User fit-verified 26 mm OLED; front/top header GND VCC SCL SDA" (at 0 0 0) (effects (font (size 1.27 1.27)) (hide yes))) +(symbol "OLED_I2C_26mm_0_1" (rectangle (start -10.16 7.62) (end 10.16 -7.62) (stroke (width 0.254) (type default)) (fill (type background)))) +(symbol "OLED_I2C_26mm_1_1" +(pin power_in line (at -15.24 3.81 0) (length 5.08) (name "GND" (effects (font (size 1.016 1.016)) )) (number "1" (effects (font (size 1.016 1.016)) ))) +(pin power_in line (at -15.24 1.27 0) (length 5.08) (name "VCC" (effects (font (size 1.016 1.016)) )) (number "2" (effects (font (size 1.016 1.016)) ))) +(pin input line (at -15.24 -1.27 0) (length 5.08) (name "SCL" (effects (font (size 1.016 1.016)) )) (number "3" (effects (font (size 1.016 1.016)) ))) +(pin bidirectional line (at -15.24 -3.81 0) (length 5.08) (name "SDA" (effects (font (size 1.016 1.016)) )) (number "4" (effects (font (size 1.016 1.016)) ))) +) +) +(symbol "SW_NO" (pin_names (offset 0.762)) (in_bom yes) (on_board yes) +(property "Reference" "SW" (at 0 7.62 0) (effects (font (size 1.27 1.27)) )) +(property "Value" "SW_NO" (at 0 5.08 0) (effects (font (size 1.27 1.27)) )) +(property "Footprint" "Button_Switch_THT:SW_TH_Tactile_Omron_B3F-100x" (at 0 0 0) (effects (font (size 1.27 1.27)) (hide yes))) +(property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) (hide yes))) +(property "Description" "Normally open contact; footprint duplicates pads 1 and 2 for internally common terminal pairs" (at 0 0 0) (effects (font (size 1.27 1.27)) (hide yes))) +(symbol "SW_NO_0_1" (polyline (pts (xy -2.54 0) (xy 2.54 1.524)) (stroke (width 0.254) (type default)) (fill (type none)))(circle (center -2.54 0) (radius 0.35) (stroke (width 0.1524) (type default)) (fill (type none)))(circle (center 2.54 0) (radius 0.35) (stroke (width 0.1524) (type default)) (fill (type none)))) +(symbol "SW_NO_1_1" +(pin passive line (at -5.08 0 0) (length 2.54) (name "~" (effects (font (size 1.016 1.016)) )) (number "1" (effects (font (size 1.016 1.016)) ))) +(pin passive line (at 5.08 0 180) (length 2.54) (name "~" (effects (font (size 1.016 1.016)) )) (number "2" (effects (font (size 1.016 1.016)) ))) +) +) +(symbol "R" (pin_names (offset 0.762)) (in_bom yes) (on_board yes) +(property "Reference" "R" (at 0 6.096 0) (effects (font (size 1.27 1.27)) )) +(property "Value" "R" (at 0 3.556 0) (effects (font (size 1.27 1.27)) )) +(property "Footprint" "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal" (at 0 0 0) (effects (font (size 1.27 1.27)) (hide yes))) +(property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) (hide yes))) +(property "Description" "Resistor, axial DIN0207 footprint; exact MPN pending" (at 0 0 0) (effects (font (size 1.27 1.27)) (hide yes))) +(symbol "R_0_1" (rectangle (start -2.54 1.016) (end 2.54 -1.016) (stroke (width 0.254) (type default)) (fill (type background)))) +(symbol "R_1_1" +(pin passive line (at -5.08 0 0) (length 2.54) (name "~" (effects (font (size 1.016 1.016)) )) (number "1" (effects (font (size 1.016 1.016)) ))) +(pin passive line (at 5.08 0 180) (length 2.54) (name "~" (effects (font (size 1.016 1.016)) )) (number "2" (effects (font (size 1.016 1.016)) ))) +) +) +) diff --git a/hardware/PCB/Carrier.pretty/HW678_2x22_Provisional.kicad_mod b/hardware/PCB/Carrier.pretty/HW678_2x22_Provisional.kicad_mod new file mode 100644 index 0000000..4c89b25 --- /dev/null +++ b/hardware/PCB/Carrier.pretty/HW678_2x22_Provisional.kicad_mod @@ -0,0 +1,56 @@ +(footprint "HW678_2x22_Provisional" + (version 20260206) + (generator "pcbnew") + (layer "F.Cu") + (descr "HW-678, component/top view antenna up USB down; origin pad 1; left top-bottom 1..22, right top-bottom 23..44; only header centres verified; no GPIO mapping, outline, courtyard or antenna keepout; PROVISIONAL connector fit: 1.70 mm pads / 1.00 mm drills from installed KiCad PinHeader_1x04_P2.54mm_Vertical, awaiting selected actual pin/socket datasheet") + (tags "module provisional THT") + (attr through_hole) + (property "Reference" "REF**" (at 12.7 -3) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) + (property "Value" "HW678_2x22_Provisional" (at 12.7 57) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15)))) + (fp_text user "PROVISIONAL CONNECTOR FIT" (at 12.7 25) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15)))) + (fp_text user "ANTENNA UP / USB DOWN" (at 12.7 28) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15)))) + (pad "1" thru_hole rect (at 0.00 0.00) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "2" thru_hole circle (at 0.00 2.54) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "3" thru_hole circle (at 0.00 5.08) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "4" thru_hole circle (at 0.00 7.62) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "5" thru_hole circle (at 0.00 10.16) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "6" thru_hole circle (at 0.00 12.70) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "7" thru_hole circle (at 0.00 15.24) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "8" thru_hole circle (at 0.00 17.78) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "9" thru_hole circle (at 0.00 20.32) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "10" thru_hole circle (at 0.00 22.86) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "11" thru_hole circle (at 0.00 25.40) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "12" thru_hole circle (at 0.00 27.94) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "13" thru_hole circle (at 0.00 30.48) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "14" thru_hole circle (at 0.00 33.02) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "15" thru_hole circle (at 0.00 35.56) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "16" thru_hole circle (at 0.00 38.10) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "17" thru_hole circle (at 0.00 40.64) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "18" thru_hole circle (at 0.00 43.18) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "19" thru_hole circle (at 0.00 45.72) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "20" thru_hole circle (at 0.00 48.26) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "21" thru_hole circle (at 0.00 50.80) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "22" thru_hole circle (at 0.00 53.34) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "23" thru_hole circle (at 25.40 0.00) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "24" thru_hole circle (at 25.40 2.54) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "25" thru_hole circle (at 25.40 5.08) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "26" thru_hole circle (at 25.40 7.62) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "27" thru_hole circle (at 25.40 10.16) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "28" thru_hole circle (at 25.40 12.70) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "29" thru_hole circle (at 25.40 15.24) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "30" thru_hole circle (at 25.40 17.78) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "31" thru_hole circle (at 25.40 20.32) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "32" thru_hole circle (at 25.40 22.86) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "33" thru_hole circle (at 25.40 25.40) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "34" thru_hole circle (at 25.40 27.94) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "35" thru_hole circle (at 25.40 30.48) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "36" thru_hole circle (at 25.40 33.02) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "37" thru_hole circle (at 25.40 35.56) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "38" thru_hole circle (at 25.40 38.10) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "39" thru_hole circle (at 25.40 40.64) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "40" thru_hole circle (at 25.40 43.18) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "41" thru_hole circle (at 25.40 45.72) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "42" thru_hole circle (at 25.40 48.26) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "43" thru_hole circle (at 25.40 50.80) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "44" thru_hole circle (at 25.40 53.34) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) +) diff --git a/hardware/PCB/Carrier.pretty/MAX3243_Reference_Provisional.kicad_mod b/hardware/PCB/Carrier.pretty/MAX3243_Reference_Provisional.kicad_mod new file mode 100644 index 0000000..a0c896b --- /dev/null +++ b/hardware/PCB/Carrier.pretty/MAX3243_Reference_Provisional.kicad_mod @@ -0,0 +1,34 @@ +(footprint "MAX3243_Reference_Provisional" + (version 20260206) + (generator "pcbnew") + (layer "F.Cu") + (descr "PROVISIONAL female 5988 CAD reference / VERIFY MALE 6253 geometry and pad map. Top view DE9 toward -Y; origin JP2 pin 1. Female reference: 1 Vin, 2 GND, 3 DCD, 4 RX, 5 TX, 6 DTR, 7 DSR, 8 RTS, 9 CTS, 10 RI, 11 VLD, 12 OFF. PROVISIONAL connector fit: carrier pads 1.70 mm / drill 1.00 mm. No verified DE9 envelope or courtyard. CAD-derived outline: Limor Fried/Ladyada for Adafruit Industries, CC BY-SA 3.0; see rs232-footprint-notes.md") + (tags "MAX3243 module female5988 reference male6253 provisional THT") + (attr through_hole) + (property "Reference" "REF**" (at 13.97 -23) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) + (property "Value" "MAX3243_Reference_Provisional" (at 13.97 -20.5) (layer "F.Fab") (effects (font (size 0.8 0.8) (thickness 0.12)))) + (fp_text user "PROVISIONAL" (at 13.97 -16) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) + (fp_text user "FEMALE CAD REF" (at 13.97 -14) (layer "F.SilkS") (effects (font (size 0.8 0.8) (thickness 0.12)))) + (fp_text user "VERIFY MALE" (at 13.97 -12.3) (layer "F.SilkS") (effects (font (size 0.8 0.8) (thickness 0.12)))) + (fp_text user "1" (at 0 1.7) (layer "F.SilkS") (effects (font (size 0.8 0.8) (thickness 0.12)))) + (fp_line (start 29.845 0.127) (end 29.845 -26.67) (stroke (width 0.1) (type solid)) (layer "F.Fab")) + (fp_line (start 29.845 -26.67) (end -1.905 -26.67) (stroke (width 0.1) (type solid)) (layer "F.Fab")) + (fp_line (start -1.905 -26.67) (end -1.905 0.127) (stroke (width 0.1) (type solid)) (layer "F.Fab")) + (fp_arc (start -1.905 0.127) (mid -1.161051224 1.923051224) (end 0.635 2.667) (stroke (width 0.1) (type solid)) (layer "F.Fab")) + (fp_line (start 0.635 2.667) (end 27.305 2.667) (stroke (width 0.1) (type solid)) (layer "F.Fab")) + (fp_arc (start 27.305 2.667) (mid 29.101051224 1.923051224) (end 29.845 0.127) (stroke (width 0.1) (type solid)) (layer "F.Fab")) + (pad "1" thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "2" thru_hole circle (at 2.54 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "3" thru_hole circle (at 5.08 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "4" thru_hole circle (at 7.62 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "5" thru_hole circle (at 10.16 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "6" thru_hole circle (at 12.7 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "7" thru_hole circle (at 15.24 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "8" thru_hole circle (at 17.78 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "9" thru_hole circle (at 20.32 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "10" thru_hole circle (at 22.86 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "11" thru_hole circle (at 25.4 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "12" thru_hole circle (at 27.94 0) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "" np_thru_hole circle (at 1.905 -8.763) (size 3 3) (drill 3) (layers "*.Cu" "*.Mask")) + (pad "" np_thru_hole circle (at 26.035 -8.763) (size 3 3) (drill 3) (layers "*.Cu" "*.Mask")) +) diff --git a/hardware/PCB/Carrier.pretty/OLED_26mm_I2C_Provisional.kicad_mod b/hardware/PCB/Carrier.pretty/OLED_26mm_I2C_Provisional.kicad_mod new file mode 100644 index 0000000..e31e2dc --- /dev/null +++ b/hardware/PCB/Carrier.pretty/OLED_26mm_I2C_Provisional.kicad_mod @@ -0,0 +1,21 @@ +(footprint "OLED_26mm_I2C_Provisional" + (version 20260206) + (generator "pcbnew") + (layer "F.Cu") + (descr "User-verified front/display view, header at top; origin top-left PCB corner; 1 GND, 2 VCC, 3 SCL, 4 SDA; PROVISIONAL connector fit: 1.70 mm pads / 1.00 mm drills from installed KiCad PinHeader_1x04_P2.54mm_Vertical, awaiting selected actual pin/socket datasheet") + (tags "module provisional THT") + (attr through_hole) + (property "Reference" "REF**" (at 13 -2) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) + (property "Value" "OLED_26mm_I2C_Provisional" (at 13 28) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15)))) + (fp_text user "PROVISIONAL CONNECTOR FIT" (at 13 30) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15)))) + (fp_rect (start 0 0) (end 26 26) (stroke (width 0.1) (type solid)) (fill no) (layer "F.Fab")) + (fp_rect (start 1 4.5) (end 25.5 21) (stroke (width 0.1) (type dash)) (fill no) (layer "F.Fab")) + (pad "1" thru_hole rect (at 9.19 1.50) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "2" thru_hole circle (at 11.73 1.50) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "3" thru_hole circle (at 14.27 1.50) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "4" thru_hole circle (at 16.81 1.50) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (remove_unused_layers no)) + (pad "" np_thru_hole circle (at 1.75 1.75) (size 2 2) (drill 2) (layers "*.Cu" "*.Mask")) + (pad "" np_thru_hole circle (at 24.25 1.75) (size 2 2) (drill 2) (layers "*.Cu" "*.Mask")) + (pad "" np_thru_hole circle (at 1.75 24.25) (size 2 2) (drill 2) (layers "*.Cu" "*.Mask")) + (pad "" np_thru_hole circle (at 24.25 24.25) (size 2 2) (drill 2) (layers "*.Cu" "*.Mask")) +) diff --git a/hardware/PCB/README.md b/hardware/PCB/README.md new file mode 100644 index 0000000..07ceaa4 --- /dev/null +++ b/hardware/PCB/README.md @@ -0,0 +1,261 @@ +# KiCad 10 module carrier — schematic and routed PCB draft + +Open **`serial-carrier.kicad_pro`** in KiCad 10, then open +**`serial-carrier.kicad_sch`**. A readable export is **`serial-carrier.pdf`**. +This is a native, editable schematic with actual connected nets, not an image +or a SKiDL-only netlist. **`serial-carrier.kicad_pcb` now contains a routed, +82 × 80 mm two-copper-layer carrier draft.** It is **not fabrication-ready**. +See **`pcb-draft-notes.md`** for placement, chosen dimensions/rules, provisional +mechanical assumptions and validation. A review drawing is `pcb-placement-draft.pdf`. + +The schematic contains the complete ESP32 development-board interface, MAX3243 +breakout logic interface, I²C OLED, three Omron B3F-1000 buttons and three 2.2 kΩ +button pull-ups. USB connectors, regulator, reset/boot circuit, DE-9 and MAX3243 +charge pump are already on their respective modules and are not duplicated on +the carrier. All 3.3 V and ground connections are explicit named nets. + +## Files and use + +| File | Purpose | +|---|---| +| `serial-carrier.kicad_pro`, `serial-carrier.kicad_sch` | Native KiCad project and A3 single-sheet schematic | +| `serial-carrier.pdf` | Schematic review/print export | +| `serial-carrier.kicad_pcb` | Routed 82 × 80 mm stepped, two-copper-layer PCB draft | +| `pcb-draft-notes.md`, `pcb-placement-draft.pdf` | PCB design decisions/limits and 1:1 placement review | +| `validation/pcb-draft.png`, `validation/pcb-draft-3d.png` | Copper/fab preview and carrier-only 3D render | +| `validate_pcb_draft.py` | Fresh schematic-to-PCB net checks, bounds/layers and DRC/parity report | +| `generate_pcb_draft.py`, `route_pcb_draft.py` | Optional destructive-regeneration tools with explicit overwrite guards | +| `Carrier.kicad_sym`, `sym-lib-table` | Project-local module, switch and resistor symbols | +| `Carrier.pretty/`, `fp-lib-table` | OLED/ESP32/RS-232-reference provisional footprints; standard KiCad 10 switch/resistor/mounting-hole library references | +| `oled-fit-check.svg` | User-fit-verified OLED mechanical template | +| `footprint-notes.md`, `rs232-footprint-notes.md` | Footprint origins, provisional pad/drill choices, validation and RS-232 adaptation attribution | +| `adafruit-research.md`, `button-notes.md`, `reference/` | Manufacturer evidence, pad maps and source/license records | +| `bom-draft.csv` | Draft procurement list and unresolved selections | +| `validate_schematic.py`, `validation/` | Repeatable netlist/firmware/ERC checks and exported evidence | +| `validate_footprints.py` | Native KiCad footprint geometry regression checks via system Python/pcbnew | +| `generate_schematic.py` | Optional stdlib-only initial design generator; not needed to open/edit in KiCad | + +Keep these files together so project-relative libraries resolve. Standard KiCad +10 footprint libraries must be installed for the THT buttons, resistors and mounting holes. +SKiDL 2.3.0 is installed, but no SKiDL dependency is required for this native design. + +**Normal validation from the repository root:** + +```sh +python3 hardware/PCB/validate_schematic.py +``` + +This checks the current schematic without regenerating it, exports its netlist, +runs KiCad ERC, checks all 17 connected nets and all 15 firmware GPIO assignments, +and refreshes PDF/SVG review exports. It requires Python 3 and `kicad-cli`. +The expected-net snapshot records the initial design contract; intentional wiring +changes need a deliberate update to the checks and snapshot. + +**Do not casually rerun `generate_schematic.py`:** it overwrites the schematic, +symbol library, library tables and expected-net snapshot, discarding subsequent +manual edits to those files. It preserves existing project settings and does not +modify footprints. The generated KiCad files are the editable design artifacts. + +## Schematic conventions and design decisions + +- U1 numbering is project-specific: viewed from the component side, antenna up + and USB down, left row is 1–22 and right row is 23–44, both top-to-bottom. + These numbers map directly to the local HW678 footprint, not to GPIO numbers + or the official DevKit header reference designators. Signal order was transcribed + from the user-supplied component-side board-label photos; the user confirmed + matching board markings. This is photo/label evidence, not a continuity test: + verify actual pin-to-function mapping before release, especially on clones. +- DS1 pins 1–4 are GND, VCC, SCL, SDA, front/display view with header at top. +- U2 pin numbering follows published Adafruit **5988 female** CAD as a provisional + reference for the selected **6253 male** module. Its footprint is deliberately + **unassigned in the schematic** until the actual male header and mechanics are + verified. The PCB draft assigns `Carrier:MAX3243_Reference_Provisional` on the + PCB only, causing one documented footprint-parity warning. Its reference nets + are routed for review, not male-board qualification. See `adafruit-research.md` + and `pcb-draft-notes.md`; this is not a generic DE-9 footprint. +- No-connect crosses mean unused on the carrier, not disconnected internally. + Native USB GPIO19/20, UART0 GPIO43/44, memory-conflicting GPIO35–37 and the 5 V + header are not connected to carrier circuitry. +- U1 pin 1 (3V3) and pin 22 (GND) model the onboard supply as power outputs for + ERC; the other duplicate rail pins are passive. This does not verify the + regulator's capacity or USB power isolation. GPIO9 is modeled as a programmable + bidirectional pad; firmware **must use open-drain mode** for OFF. ERC does not + enforce that configuration or model the breakout's internal OFF pull-up. +- Selected buttons are Omron B3F-1000 with their verified KiCad THT footprint. + Added R1–R3, **2.2 kΩ, 1%, at least 0.125 W**, from each button input to 3.3 V. + They provide nominal 1.5 mA contact current / 4.95 mW dissipation while pressed, + rather than relying on the internal pull-up for the silver-contact rated load. + Firmware's internal pull-ups and debouncing remain enabled; no firmware changes + are required. Final supply tolerance/load budget still needs checking. + DIN0207 axial footprints are selected; exact resistor MPNs remain pending. +- External I²C pull-ups are **not assigned guessed values**. Verify OLED onboard + pull-ups, resistance and rail before electrical sign-off and add appropriately + sized carrier pull-ups if needed. The OLED must be powered from 3.3 V. + +## Validation status + +KiCad CLI 10.0.6 loaded the schematic and exported PDF, SVG and XML netlist. +ERC reported **zero errors/warnings**, with no project exclusions added. Exact +net memberships, all 44 U1 pins and firmware GPIO assignments were checked. +The PDF was rendered and visually inspected for layout/readability. Both local +footprints loaded in KiCad's native footprint loader. Two retained regression tests +passed with `/usr/bin/python3 -B hardware/PCB/validate_footprints.py`; the binding +emits startup PROPERTY_ENUM assertions but completes the checks. See +`footprint-notes.md` for scope and limitations. + +OLED PCB/header/display/mounting-hole geometry was physically fit-verified by +the user. This does **not** validate connector drills, male RS-232 geometry, +electrical operation, power budget, procurement or fabrication. + +The routed PCB draft has **0 physical DRC violations and 0 unconnected items**; +a fresh netlist-to-PCB check passes. One deliberate U2 footprint-parity warning +remains (PCB reference footprint versus blank schematic assignment). No added +DRC exclusions hide this warning. Missing courtyards are ignored by default DRC +and remain a manual release check. Run `/usr/bin/python3 -B +hardware/PCB/validate_pcb_draft.py` from the repository root; see +`pcb-draft-notes.md` for the complete verification scope and remaining gates. +No firmware build or device tests were run: this PCB work did not modify firmware. + +## Evidence and components + +Repository sources: `../../docs/wiring.md`, `../../src/board_pins.h`, +`../../docs/electrical_tests.md`, and `../../README.md`. + +| Assembly | Repository identification | Footprint status | +|---|---|---| +| ESP32 development board | User confirmed HW-678 V0.0.0 markings and S3-N16R8 shield, two USB-C ports | Two 22-pin rows; nominal 2.54 mm pitch and 25.40 mm row spacing supported by simultaneous breadboard fit. Mechanical outline registration and socket/drill selection remain pending. | +| RS-232 module | Adafruit MAX3243 full-pinout breakout; male is product 6253, female is 5988 | Published female CAD pin map and geometry verified; male mapping/fit remains provisional. Reference footprint used on PCB only; schematic assignment remains blank. | +| Display | 128×64 yellow/blue I²C OLED, address 0x3c; Amazon ASIN B0F13SSSFB | 26 mm square board, 22.50 mm hole spacing, Ø2 mm holes and centred header 1.50 mm from top edge are user-fit-verified. Local footprint assigned; header pad/drill selection remains provisional. | +| Three buttons | Omron B3F-1000; previous, select, next; normally open to ground, active low | Datasheet and `Button_Switch_THT:SW_TH_Tactile_Omron_B3F-100x` pad mapping verified. External 2.2 kΩ pull-ups included. Live distributor stock remains unverified. | + +Adafruit manufacturer CAD starting point: +https://learn.adafruit.com/adafruit-rs-232-full-pinout-level-shifter-breakout/downloads + +Published female-module Eagle CAD and its header map were retrieved and verified; +see `adafruit-research.md` for pinned revision, hashes, attribution and geometry. +The original files and CC BY-SA 3.0 notices are retained in `reference/`; they +remain under their upstream license. Omron reference documents retain their +manufacturer notices. No male-specific module footprint is claimed verified. + +## Verified logical connections for the existing firmware profile + +This table uses signal names, **not physical connector positions**. The schematic +and its local symbols additionally capture the project's physical pad numbering. +The wiring guide warns that compatible ESP32 boards may have different layouts. + +| ESP32 connection | Peripheral connection | +|---|---| +| 3V3 | RS-232 Vin; existing I²C OLED VCC | +| GND | RS-232 GND; OLED GND; one contact of each button | +| GPIO17 | RS-232 TX | +| GPIO18 | RS-232 RX | +| GPIO15 | RS-232 RTS | +| GPIO16 | RS-232 CTS | +| GPIO7 | RS-232 DTR | +| GPIO5 | RS-232 DSR | +| GPIO4 | RS-232 DCD | +| GPIO6 | RS-232 RI | +| GPIO8 | RS-232 VLD | +| GPIO9 | RS-232 OFF (active-low shutdown; open-drain drive) | +| GPIO11 | Existing I²C OLED SDA | +| GPIO12 | Existing I²C OLED SCL | +| GPIO10 | Previous/back switch to GND | +| GPIO13 | Select/confirm switch to GND | +| GPIO14 | Next switch to GND | + +## Electrical constraints from the repository + +- Keep UART0 / GPIO43 and GPIO44 available through the onboard USB-UART bridge. +- Reserve GPIO19 and GPIO20 for onboard native USB. +- Existing firmware profile powers RS-232 Vin and OLED VCC from 3.3 V, not 5 V. +- Confirm the exact development board's regulator capacity and USB power-path + behavior before finalizing the power design, especially with both USB ports attached. +- Display pull-up presence, resistance and termination rail must be checked on + the actual module. Do not select external pull-up values without this information. +- Firmware enables internal button pull-ups; this carrier additionally uses 2.2 kΩ + external pull-ups for the selected buttons' contact-current requirement. +- RS-232 OFF uses the breakout's onboard pull-up; GPIO9 releases it to enable. +- The breakout is not galvanically isolated; signal grounds are common. +- Preserve access to both development-board USB connectors and account for the + antenna keepout using the exact board/module documentation. + +## User-confirmed design direction + +- ESP32 purchase: https://www.amazon.de/dp/B0F3XMYYQY +- OLED purchase: https://www.amazon.de/dp/B0F13SSSFB — I²C, not SPI. +- Both Amazon URLs returned an access-check page on inspection; the ASINs alone + do not establish a verified manufacturer drawing or footprint. +- Use the male Adafruit breakout. User reports male/female board dimensions match; + verify the selected male board against its manufacturer CAD. +- Carrier for complete modules: soldered module headers for final assembly, + sockets for beta testing without a case. Header pitch, row spacing, drill size + and socket clearance must be validated against selected hardware. +- Power only through the ESP32 development board's USB connectors, typically a + powerbank or the serial peer's USB port, with common ground. Do not introduce + another carrier power input or assume simultaneous USB supplies are isolated. +- Select readily available THT buttons; the existing random switches need not be reused. +- Case will be 3D-printed after PCB finalization. Include mounting provisions in + the layout, but screw size, hole diameter and insert bosses are not yet selected. + +## User-supplied mechanical evidence + +- ESP32 listing pictures show HW-678 V0.0.0; user confirms matching markings and + actual shield S3-N16R8. Disregard the listing picture's N8R2 marking for memory + identification and its erroneous USB labels: native USB is GPIO19 D− / GPIO20 D+. +- ESP32 raw measurements: header first-to-last centres initially 52.6 mm, revised + to 52.93 mm; row spacing measured 25.00 mm. User subsequently confirmed both + rows fit a standard breadboard simultaneously without forcing. Use nominal + 2.54 mm pitch (53.34 mm over 21 intervals) and 25.40 mm row spacing based on + that fit check, not the raw caliper measurements. Verify with a 1:1 print before fabrication. +- ESP32 seller drawing states 28 mm width and annotates 63 mm length; its 20 mm + arrow is not header row spacing. Antenna extent and header-to-outline offsets + are not fully dimensioned. +- OLED actual PCB outline measured by user: 26 × 26 mm, superseding the seller's + 28.7 × 27.8 mm dimensions. Seller's 4.1 mm height remains unverified. +- OLED front view, connector at top: GND, VCC, SCL, SDA from left to right, + confirmed on actual module. Raw first-to-last span revised from 7 mm to 7.49 mm; + user confirms standard breadboard fit and agrees nominal pitch is 2.54 mm + (7.62 mm span). +- OLED mounting-hole diameter measured as 2 mm. User approved the latest edge + measurements as superseding the earlier 22.16 mm hole-spacing measurement: + centres are 1.75 mm from adjacent edges, giving 22.50 mm spacing in both axes. +- User verified the template's PCB outline and mounting-hole placement against + the actual OLED module: both fit perfectly. Header-pin centres were subsequently + corrected to 1.50 mm from the top PCB edge, superseding 0.75 mm. The header row + is therefore 0.25 mm nearer the top edge than the upper mounting-hole centres. +- User measured the display outline margins: top 4.5 mm, bottom 5 mm, left 1 mm, + right 0.5 mm. On the 26 mm PCB this defines a 24.5 × 16.5 mm rectangle from + (1, 4.5) to (25.5, 21), shown dashed in the template. This records the supplied + display boundary, not an independently verified active-pixel area or case cutout. +- User subsequently confirmed the revised template is "about a perfect fit", + validating the PCB outline, mounting-hole placement, corrected 1.50 mm header + position and display outline against the actual module. This is a user-reported + mechanical fit check, not electrical or fabrication validation. +- User explicitly approved a horizontally centred header, superseding the earlier + approximate 7.33 mm hole-to-pin measurements. +- Approved coordinates in mm, viewed from the display side with the header at + the top, origin at the top-left PCB corner, X right and Y down: + GND (9.19, 1.50), VCC (11.73, 1.50), SCL (14.27, 1.50), SDA (16.81, 1.50). + Mounting-hole centres: (1.75, 1.75), (24.25, 1.75), (1.75, 24.25), + (24.25, 24.25), each diameter 2 mm. Board outline: (0, 0) to (26, 26). +- `oled-fit-check.svg` is a 1:1 mechanical template of that geometry. Print at + 100%, without fit-to-page, and verify its 20 mm scale before checking the module. + Crosshairs denote header centres, not specified pad or drill diameters. This + template is not a KiCad footprint or a fabrication file. + +## Remaining mechanical/electrical checks + +1. OLED outline, mounting-hole placement, revised header position and display + outline are user fit-verified. Select carrier header/socket pads and drills + from the actual connector drawings. +2. Before final module outlines/courtyards, establish their registration to header + centres, connector overhang and display position from drawings or measurements. +3. Verify power-path schematic/regulator capacity and OLED pull-up implementation. + Photos alone do not establish those electrical properties. + +The native schematic, local libraries and routed two-layer PCB draft are present. +Before fabrication, finish the above checks, qualify the male RS-232 module map +and footprint, and confirm procurement. The carrier now proposes an 82 × 80 mm +stepped outline and four Ø3.2 mm M3 mounting holes; case hardware is not yet fixed. +The PCB's RF reserve is a draft design allocation, not a verified module antenna +keepout. Module/USB/DE-9 clearances must still be established from actual hardware. diff --git a/hardware/PCB/adafruit-research.md b/hardware/PCB/adafruit-research.md new file mode 100644 index 0000000..f90f847 --- /dev/null +++ b/hardware/PCB/adafruit-research.md @@ -0,0 +1,142 @@ +# Adafruit MAX3243 breakout: authoritative CAD header research + +Research date: 2026-09-20. Scope: source retrieval and pad/geometry extraction only; no project schematic or layout modified. + +## Critical product distinction + +**Product 5988 is the DE-9 female version. The male version is product 6253.** The product-5988 page's male variant link goes to `/product/6253`; each product description explicitly identifies its connector gender. Both link to the same Learn guide. Do not describe the downloaded CAD as verified male-specific CAD: its connector is `X2`, value `DE9-F`, package `F09HP`, and the repository README identifies product 5988. + +The exact header map below is proven for the published 5988 board. It is useful reference for the family, but identical male-board geometry/pad numbering has **not** been established by a male-specific CAD file or physical measurement. Confirm the actual 6253 module before releasing a male carrier footprint. No inference from connector gender or a generic DE-9 footprint is substituted for that check. + +## Provenance and downloaded originals + +Authoritative chain: + +1. [Adafruit Learn downloads](https://learn.adafruit.com/adafruit-rs-232-full-pinout-level-shifter-breakout/downloads) links to the Eagle repository below, a TI datasheet, fab print and 3D models. +2. [Adafruit PCB repository](https://github.com/adafruit/Adafruit-RS-232-Level-Shifter-Breakout-PCB). +3. Retrieved `main` commit **`63c6200bb3ef17d491089cfa6441b1810d79bb20`**, committed 2024-08-12T22:42:27Z. All four local originals were downloaded from this immutable revision, not a moving branch. +4. [Product 5988, female](https://www.adafruit.com/product/5988), [product 6253, male](https://www.adafruit.com/product/6253), and [Learn pinouts](https://learn.adafruit.com/adafruit-rs-232-full-pinout-level-shifter-breakout/pinouts) corroborate identity and signal names. + +Local files in `reference/`, unchanged upstream contents: + +| File | SHA-256 | +|---|---| +| `Adafruit RS-232 Full Pinout Level-Shifter Breakout.brd` | `6a7b35ef909f5a2d243c326c34db3957aaa01275bf2aac8e0c749ff18162e870` | +| `Adafruit RS-232 Full Pinout Level-Shifter Breakout.sch` | `4efbbe0ad14194e4e4563dd5f7dac007dfd52eba636f7390ffb822f3e81cd896` | +| `README.md` | `2825ba741a8ce83abdaf2c7cb9170641473357630ccbee40a0016dcdb5cd80bb` | +| `license.txt` | `075dad5e5fc96c27014fabc269f4f5732909cffd178a486f546d982b6cf86b74` | + +Raw URL prefix for each filename (URL-encode spaces): + +`https://raw.githubusercontent.com/adafruit/Adafruit-RS-232-Level-Shifter-Breakout-PCB/63c6200bb3ef17d491089cfa6441b1810d79bb20/` + +**License:** upstream `license.txt` is **Creative Commons Attribution-ShareAlike 3.0 Unported (CC BY-SA 3.0)**. README attribution: “Designed by Limor Fried/Ladyada for Adafruit Industries.” README explicitly requires all its preceding text in redistribution; the full original README and license are therefore retained. Preserve these notices when redistributing CAD and comply with applicable attribution/share-alike obligations for adaptations. The CAD-derived content of this report is attributed to that design and provided under CC BY-SA 3.0. + +The guide also links [5988 3D CAD](https://github.com/adafruit/Adafruit_CAD_Parts/tree/main/5988%20RS-232%20Level%20Shifter). Its directory listing contains `.f3d`, `.step`, `.stl`, and `.jpg`; these were **not downloaded or used for measurements**, and their licensing was not independently assessed. No male-specific 3D model was verified in this research. + +## Exact header numbering and net map + +Source: Eagle XML `drawing/board/elements/element[@name='JP2']`, embedded `microbuilder` package `1X12_ROUND_76MIL`, and `drawing/board/signals/signal/contactref`. Cross-checked against schematic `JP2`, deviceset `HEADER-1X12`, selected device `76MIL`: symbol pin N maps directly to physical pad N. + +**Viewing convention:** component/top view, DE-9 pointing toward the top of the page (+Y), logic header along the bottom. X increases rightward, Y upward. The origin is the lower-left bounding-box corner of the bare PCB (the corner itself is rounded). These are Eagle board coordinates in **millimetres**, not a mating-face view and not a bottom view. + +```text + DE-9 / +Y + +-----------------------+ + | | + | o o | module mounting holes + | | + | 1 2 3 ... 12 | JP2, y = 2.667 mm + +-----------------------+ + Vin OFF + +X -> +``` + +| JP2 physical pad | Label / function | CAD net | X (mm) | Y (mm) | MAX3243 IC1 pad | DE-9 X2 pad via level shifter | +|---:|---|---|---:|---:|---:|---:| +| 1 | Vin | VCC | 1.905 | 2.667 | 26 | — | +| 2 | GND | GND | 4.445 | 2.667 | 25 | 5 (direct ground) | +| 3 | DCD | DCD | 6.985 | 2.667 | 15 | 1 | +| 4 | RX | RXD | 9.525 | 2.667 | 16 | 2 | +| 5 | TX | TXD | 12.065 | 2.667 | 13 | 3 | +| 6 | DTR | DTR | 14.605 | 2.667 | 14 | 4 | +| 7 | DSR | DSR | 17.145 | 2.667 | 17 | 6 | +| 8 | RTS | RTS | 19.685 | 2.667 | 12 | 7 | +| 9 | CTS | CTS | 22.225 | 2.667 | 19 | 8 | +| 10 | RI | RI | 24.765 | 2.667 | 18 | 9 | +| 11 | VLD | !INVALID | 27.305 | 2.667 | 21 | — | +| 12 | OFF | !FORCEOFF | 29.845 | 2.667 | 22 | — | + +**Left-to-right order: `Vin GND DCD RX TX DTR DSR RTS CTS RI VLD OFF`.** This is physical pad order, not the order of rows in the project's wiring table. + +At the logic header, TX/DTR/RTS are inputs to the MAX3243; RX/DCD/DSR/CTS/RI are outputs from it. Schematic gates explicitly map TX to T2IN, DTR to T1IN, RTS to T3IN, RX to R4OUT, DCD to R5OUT, DSR to R3OUT, CTS to R1OUT and RI to R2OUT. RS-232 and logic signal nets are separated by the chip; matching signal names do not mean direct continuity. + +OFF is **active low** (`!FORCEOFF`, IC1 pad 22) with 10 kΩ pull-up R1 to VCC. The Learn pinout page agrees. The upstream README and shop prose incorrectly say high shuts it down; do not propagate that prose error. VLD is `!INVALID`, high on valid input detection. Use 3.3 V Vin for this project's ESP32 interface, as already required by `docs/wiring.md`. + +## Exact published PCB geometry + +All figures below are nominal CAD dimensions, not measured tolerances. + +### Logic header JP2 + +- Single row, **12 plated through-hole pads at 2.54 mm (0.100 inch) pitch**. +- Element origin `(15.875, 2.667)`; no element rotation or mirroring (R0). +- Package local pad centres: `x = -13.970 + 2.540 × (N - 1)`, `y = 0`, N = 1…12. +- Board coordinates: `x = 1.905 + 2.540 × (N - 1)`, `y = 2.667`. +- First-to-last centre span **27.940 mm (1.100 inch)**. +- All holes: **1.000 mm drill**, explicit **1.9304 mm (76 mil) round copper diameter**. Each pad has `rot="R90"`; that does not rotate the header row or change a round pad's outline. +- Both end pad centres are **1.905 mm** from the corresponding vertical board edge. +- Row is **2.667 mm (0.105 inch)** above the lower bounding-box edge. +- No square pad-1 marker is defined by this package: identify pad 1 using Vin and the stated view, not assumed square copper. + +### Bare-board outline and mounting holes + +Source: `drawing/board/plain/wire[@layer='20']` and mounting-hole element/package definitions. + +- Bare PCB bounding box: **31.750 mm X × 29.337 mm Y** (1.250 × 1.155 inches), X = 0…31.750, Y = 0…29.337. +- Straight top edge `(0,29.337)` to `(31.750,29.337)`; square top corners. +- Bottom corners: **2.540 mm radius**, defined by 90° arcs `(0,2.540)` → `(2.540,0)` and `(29.210,0)` → `(31.750,2.540)`. +- Bottom straight edge: X = 2.540…29.210 at Y = 0. +- Module mounting holes: `U$2` at **(3.810, 11.430)** and `U$3` at **(27.940, 11.430)**. +- Both use `MOUNTINGHOLE_3.0_PLATEDTHIN`, pad `P$1`, **3.000 mm drill / 3.600 mm copper diameter**. They are plated pads, not anonymous NPTH holes, and neither appears in the board's signal contactrefs. +- Hole centre spacing **24.130 mm (0.950 inch)**; hole row is **8.763 mm** above the header row. + +For a carrier footprint using header pad 1 as `(0,0)` with Y still upward: + +- Header pads: `(2.540 × (N - 1), 0)`. +- Mounting hole centres: **(1.905, 8.763)** and **(26.035, 8.763)**. +- Bare-board bounding box: X = **−1.905…29.845**, Y = **−2.667…26.670**; retain corner arcs described above. + +If the destination CAD uses screen coordinates with Y downward, transform Y deliberately; do not silently mirror physical pad numbering. The placement side and whether the module faces up or down must be fixed before generating a carrier footprint. + +### DE-9 on the downloaded female CAD (not male qualification) + +`X2` origin `(15.875,17.907)`, R0, package `F09HP`, value `DE9-F`. + +| X2 pad | Board X (mm) | Board Y (mm) | CAD net | +|---|---:|---:|---| +| 1 | 10.3886 | 16.637 | RS_DCD | +| 2 | 13.1318 | 16.637 | RS_RXD | +| 3 | 15.8750 | 16.637 | RS_TXD | +| 4 | 18.6182 | 16.637 | RS_DTR | +| 5 | 21.3614 | 16.637 | GND | +| 6 | 11.7602 | 19.177 | RS_DSR | +| 7 | 14.5034 | 19.177 | RS_RTS | +| 8 | 17.2466 | 19.177 | RS_CTS | +| 9 | 19.9898 | 19.177 | RS_RI | +| G1 | 3.3528 | 17.907 | no signal contactref | +| G2 | 28.3972 | 17.907 | no signal contactref | + +Signal holes have 1.016 mm drill and 1.778 mm octagonal copper; shell/mechanical pads G1/G2 have 3.302 mm drill and 5.080 mm copper, spaced 25.0444 mm. Shell pads are not shown tied to GND by signal contactrefs; DE-9 pin 5 is grounded. These are **PCB solder-tail coordinates**, not front-face pin coordinates. + +The connector package's layer-21 drawing reaches local Y = 17.907, hence board Y = 35.814, beyond the board's Y = 29.337. This is library drawing evidence, **not a validated mechanical envelope**. Do not size an enclosure from silkscreen. Product pages list assembled dimensions of 33.6 × 32.0 × 14.1 mm (5988) and 33.7 × 31.8 × 14.2 mm (6253), with no coordinate/tolerance definition; these do not replace a male-specific mechanical drawing, and differ from the female library drawing extent. + +## Validation and next-use boundary + +- Parsed the actual Eagle board and schematic XML successfully using Python's standard-library XML parser. +- Joined package pad names to board signal contactrefs, applied JP2's unrotated element translation, and cross-checked schematic header numbering/net assignments. +- Extracted outline arcs, mounting-hole package dimensions, and connector pad data directly; no dimensions inferred from product photos. +- Recorded SHA-256 hashes of the downloaded originals. +- No firmware build or hardware tests performed: this task changed research/reference files only. +- **Ready:** exact published 5988 header map, pad centres, board outline and hole coordinates for CAD reference. +- **Still required for a male-module carrier release:** establish that the purchased module is 6253, verify its header order and mounting geometry against male-specific CAD or the physical module, and verify connector overhang, mating clearance, module height and mounting orientation. The shared guide alone is insufficient proof of identical male geometry. diff --git a/hardware/PCB/bom-draft.csv b/hardware/PCB/bom-draft.csv new file mode 100644 index 0000000..801ddea --- /dev/null +++ b/hardware/PCB/bom-draft.csv @@ -0,0 +1,8 @@ +References,Quantity,Description,Manufacturer,MPN or identification,Footprint,Status +U1,1,ESP32-S3 N16R8 development board,User supplied,HW-678 V0.0.0 / ASIN B0F3XMYYQY,Carrier:HW678_2x22_Provisional,Header pitch/spacing confirmed; connector drill fit and module envelope pending +U2,1,MAX3243 full-pinout RS-232 breakout male,Adafruit,6253,Carrier:MAX3243_Reference_Provisional,PCB-only reference footprint; schematic assignment blank; male header/geometry verification required +DS1,1,128x64 yellow-blue I2C OLED 26mm PCB,User supplied,ASIN B0F13SSSFB,Carrier:OLED_26mm_I2C_Provisional,Module geometry user-fit-verified; carrier header drill fit pending +SW1 SW2 SW3,3,Normally-open 6mm THT tactile switch,Omron,B3F-1000,Button_Switch_THT:SW_TH_Tactile_Omron_B3F-100x,Datasheet/footprint checked; stock unverified +R1 R2 R3,3,2.2k ohm 1 percent axial resistor at least 0.125W,TBD,TBD,Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal,Design value selected; exact MPN and body/lead fit pending +H1 H2 H3 H4,4,Proposed M3 case mounting locations with 3.2mm NPTH,TBD,TBD,MountingHole:MountingHole_3.2mm_M3,Board-only hole locations; screws and insert/standoff dimensions not selected +Assembly hardware,TBD,Module headers and optional beta-test sockets plus mounting hardware,TBD,TBD,,Not yet selected; not included in electrical component count diff --git a/hardware/PCB/button-notes.md b/hardware/PCB/button-notes.md new file mode 100644 index 0000000..e090385 --- /dev/null +++ b/hardware/PCB/button-notes.md @@ -0,0 +1,107 @@ +# Button selection: Omron B3F-1000 + +Verified 2026-09-20 against the Omron datasheet and installed KiCad libraries. This research covers three active-low GPIO-to-GND buttons. + +**Integration decision:** the A0 schematic now implements B3F-1000 switches with one **2.2 kΩ, 1%, at least 0.125 W external pull-up** per input. The lower-current/internal-pull-up-only discussion below records the selection rationale, not an unselected schematic option. Firmware is unchanged. Exact resistor MPN, supply tolerance/budget and stock remain release checks. + +## Schematic-ready recommendation + +**B3F-1000 fits the installed footprint mechanically and its normally-open contact topology matches the circuit. Low-current operation with internal pull-ups needs the qualification below.** + +For each of the three buttons: + +- Value / manufacturer part number: **B3F-1000**, Omron; standard silver-plated contacts, ivory flat plunger, no separate ground terminal. +- Symbol: **`Switch:SW_Push`** (normally open, two passive pins). +- Explicitly assign footprint: **`Button_Switch_THT:SW_TH_Tactile_Omron_B3F-100x`**. The installed symbol's default footprint field is empty. +- Symbol pin **1 → GPIO**, symbol pin **2 → GND**. The switch is nonpolar; swapping these two nets is electrically equivalent. + +| Function | Pin 1 net | Pin 2 net | +|---|---|---| +| Previous/back | GPIO10 | GND | +| Select/confirm | GPIO13 | GND | +| Next | GPIO14 | GND | + +GPIO assignments verified in `src/board_pins.h`. The PCB README specifies normally-open buttons to GND with internal pull-ups. Released = high; pressed = low. No voltage source connects directly through the switch: any external pull-up goes through a resistor to 3.3 V. + +## Exact terminal and pad mapping + +The installed footprint has **four physical holes but only two distinct electrical pad numbers: `1,1,2,2`**, not four uniquely numbered pads. The installed `SW_Push` symbol has pin 1 at the left and pin 2 at the right in its default orientation; pin numbers are hidden by the symbol. + +Unrotated footprint, front/top view; local coordinates in mm, positive Y downward: + +```text + 6.5 mm +KiCad pad 1 (0,0) ----------- KiCad pad 1 (6.5,0) +Omron terminal 4 Omron terminal 3 + NO + contact 4.5 mm +Omron terminal 2 Omron terminal 1 +KiCad pad 2 (0,4.5) --------- KiCad pad 2 (6.5,4.5) +``` + +The horizontal connections above are permanent internal connections; pressing joins the two rows. Omron datasheet **page 4**, upper-left **“Terminal Arrangement/Internal Connections (Top View)”**, explicitly shows terminals **4–3 common** and **2–1 common**. This maps to KiCad's upper pair numbered 1 and lower pair numbered 2 when aligned as shown. **Omron terminal 1 is not KiCad pad 1 in this orientation.** The manufacturer's separate bottom-view numbering sketch must not be mistaken for a top view. Omron states terminal numbers are not marked on the switches. A 180° insertion swaps the two electrical sides without affecting this nonpolar circuit. + +Both pads numbered 1 receive the symbol pin-1 net; both pads numbered 2 receive pin-2's net. Do not attach a four-unique-pin symbol to this footprint without an explicit remapping. Connecting GPIO and GND to two terminals within the same common pair would permanently ground the GPIO. + +The footprint sets `duplicate_pad_numbers_are_jumpers no`; do not assume PCB routing software will treat the internal metal as a routing jumper. Route/check the duplicate-pad nets normally. + +## Manufacturer dimensions and ratings + +Source: Omron B3F datasheet, ordering table p. 1, ratings/operating characteristics p. 3, B3F-1000 drawing p. 4. Dimensions below are mm. + +| Item | Datasheet specification | +|---|---| +| Body | 6 ±0.2 × 6 ±0.2 | +| Overall height above seating plane | 4.3 ±0.2 | +| Plunger diameter | 3.5 | +| Terminal row spacing | 4.5 ±0.2 | +| Formed terminal span at hole-entry region | 6.5 ±0.5 | +| Maximum-width dimension shown across formed leads | 7.7 ±0.5 | +| Lead projection below seating plane | 3.5 | +| Lead thickness / width callouts | 0.3 / 0.7 | +| Recommended PCB hole-centre grid | 6.5 ±0.1 × 4.5 ±0.1 | +| Recommended PCB holes | Four, diameter 1 ±0.1; reference drawing for PCB thickness 1.6 | +| General dimensional tolerance | ±0.4 unless otherwise specified | +| Contact form | SPST-NO | +| Rated resistive load, standard silver version | **1–50 mA at 3–24 VDC** | +| Minimum applicable load | **10 µA at 1 VDC, reference value** | +| Initial contact resistance | 100 mΩ maximum | +| Bounce | 5 ms maximum | +| Operating force | 0.98 ±0.29 N (100 ±30 gf) | +| Release force | 0.2 N minimum | +| Pretravel | 0.25 +0.2/−0.1 | +| Durability for B3F-1000, 0.98 N | 1,000,000 operations minimum | +| Protection / washing | IP00 / washing not possible | + +### Installed footprint comparison + +Inspected `/usr/share/kicad/footprints/Button_Switch_THT.pretty/SW_TH_Tactile_Omron_B3F-100x.kicad_mod` (file format version `20260206`, generator version `10.0`) and `/usr/share/kicad/symbols/Switch.kicad_sym`. + +- Hole centres: `(0,0)`, `(6.5,0)`, `(0,4.5)`, `(6.5,4.5)` — match Omron's nominal PCB grid. +- All four plated through-hole pads: circular copper diameter **1.7**, drill **1.0**, front/back copper and mask — nominal drill matches Omron's reference hole diameter. Confirm the fabricator's finished-hole tolerance when ordering. +- Fab body: `(0.25,-0.75)` to `(6.25,5.25)`, **6 × 6**, matching nominal body dimensions. +- Courtyard: `(-1.1,-1.1)` to `(7.6,5.6)`, **8.7 × 6.7**. This is a library placement boundary, not an enclosure or finger-access clearance specification. +- Footprint description specifies H4.3 mm. No physical sample fit, enclosure-height check, or independent 3D-model measurement was performed. + +## Low-current qualification / selection decision + +**Do not claim internal-pull-up operation meets the standard part's full rated-load range.** At 3.3 V, pull-up resistance greater than 3.3 kΩ gives less than 1 mA contact current. For illustration only, 45 kΩ would give about 73 µA; that is not a verified resistance specification for this board's GPIOs. + +Omron's 10 µA / 1 V minimum is explicitly a **reference value**, not an unconditional low-current reliability guarantee. B3F-1000 is a reasonable prototype choice, but internal-pull-up-only contact reliability should be qualified in the intended environment and over life. + +For a conservative silver-contact design within the stated rated load, consider **one external 2.2 kΩ pull-up to 3.3 V per button** (about 1.5 mA while pressed); verify supply/resistor tolerances and GPIO limits before adopting. This recommendation was subsequently adopted in the A0 carrier schematic; see the integration decision above. If low current is important, the datasheet also lists **B3F-1002-G** with gold contacts in the same p. 4 dimensional group, rated 100 µA–50 mA at 3–24 VDC, but with a different operating force (1.76 ±0.49 N); weak internal pull-ups are not automatically within that rated range either. It has not been selected or stock-checked here. + +Retain firmware debouncing; a mechanical switch is not bounce-free. The device is unsealed (IP00), and the datasheet prohibits washing. + +## Supply evidence + +**Live stock not verified; no supply assurance.** On 2026-09-20 a request to the [DigiKey B3F-1000 product URL](https://www.digikey.com/en/products/detail/omron-electronics-inc-emc-div/B3F-1000/33150) returned HTTP 403 / an anti-bot challenge. No quantity, price, lead time, or lifecycle status could be established from that response. Confirm the exact MPN and available quantity with a distributor before BOM release; datasheet availability is not stock evidence. + +## Evidence and remaining checks + +- [Authoritative Omron datasheet](https://omronfs.omron.com/en_US/ecb/products/pdf/en-b3f.pdf), retrieved 2026-09-20. +- [Local PDF](reference/button-omron-b3f.pdf). +- [Extracted text](reference/button-omron-b3f.txt) for searching; use the PDF for drawing interpretation. +- [Rendered page 4](reference/button-omron-b3f-page4.png), visually checked for the internal connections and dimensions. + +Before manufacturing: validate the selected pull-up strategy against supply tolerances/budget; check ERC/net assignment and PCB DRC in the actual design; confirm finished holes, enclosure/actuator access and a sample's fit/continuity; confirm procurement. This review verifies datasheet-to-library compatibility, not a completed-board electrical or mechanical test. diff --git a/hardware/PCB/footprint-notes.md b/hardware/PCB/footprint-notes.md new file mode 100644 index 0000000..e5a299b --- /dev/null +++ b/hardware/PCB/footprint-notes.md @@ -0,0 +1,105 @@ +# Provisional carrier module footprints + +These project-local footprints are in `Carrier.pretty`. They are mechanical +starting points, **not fabrication-ready connector selections**. Both are now +assigned to their matching symbols in the native schematic through the project +library tables and used in the routed PCB draft. The assembled module 3D models +are not provided. See `pcb-draft-notes.md` for placement/routing and +`rs232-footprint-notes.md` for the additional provisional RS-232 reference footprint. + +## Shared pad/drill provenance and limits + +Reference inspected locally: installed KiCad library footprint +`Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical`, file +`/usr/share/kicad/footprints/Connector_PinHeader_2.54mm.pretty/PinHeader_1x04_P2.54mm_Vertical.kicad_mod` +(format version `20260206`; local KiCad `10.0.6-1.fc44`). + +Both footprints use that reference's **1.70 × 1.70 mm plated through-hole pads, +1.00 mm drills, rectangular pad 1, and circular remaining pads**, on +`*.Cu` and `*.Mask`, with unused copper layers retained. Nominal pitch is 2.54 mm. +Only the reference's pad/drill convention is reused, not its connector body, +courtyard, or 3D model. HW678 pad 23 is circular: only overall pad 1 is rectangular. + +**PROVISIONAL connector fit — awaiting the selected actual pin/socket datasheet.** +Breadboard fit supports centre spacing, not drill size, finished-hole tolerance, +annular-ring suitability, socket body clearance, mating height, or solderability. +Validate those against the actual final headers and beta-test sockets and the PCB +fabricator's process before release. No electrical nets or ESP32 GPIO assignments +are inferred. No courtyards are supplied: module/connector assembly clearances +remain incomplete, so automated courtyard checks cannot establish fit. + +Coordinates below are millimetres, unrotated on the carrier front side, X right +and Y down. Views are not mirrored. Placement on the back side or viewing the +module from its solder side requires the appropriate KiCad transform; do not +silently reverse the numbering. + +## `Carrier:OLED_26mm_I2C_Provisional` + +Origin: top-left corner of the module PCB, viewed from the front/display side, +header at the top. User-verified geometry from the current request and the later +mechanical-evidence section of `README.md`: + +| Pad | Signal | X | Y | +|---|---|---:|---:| +| 1 | GND | 9.19 | 1.50 | +| 2 | VCC | 11.73 | 1.50 | +| 3 | SCL | 14.27 | 1.50 | +| 4 | SDA | 16.81 | 1.50 | + +- PCB boundary: (0, 0) to (26, 26), solid rectangle on `F.Fab`. + This depicts the module, not the carrier's routed edge; no `Edge.Cuts` is used. +- Four unnumbered, non-plated through holes, diameter 2.00 mm, at + (1.75, 1.75), (24.25, 1.75), (1.75, 24.25), (24.25, 24.25). + Hole centres are 1.75 mm from adjacent edges, with 22.50 mm spacing in both axes. + These transfer the verified module hole geometry to the carrier; they do not + select screws, inserts, bosses, or hardware clearance envelopes. +- Display boundary: (1, 4.5) to (25.5, 21), 24.5 × 16.5 mm, dashed on `F.Fab`. + This is the supplied display boundary, not a verified active-pixel area or case cutout. +- Pad-to-signal mapping is documented here and in the footprint description; + footprint pads themselves have numbers, not assigned nets. + +The approved geometry supersedes the earlier 22.16 mm hole-spacing measurement: +22.50 mm hole spacing, Y=1.50 mm header centres, and the centred header coordinates +above apply. See README for the user-reported successful template fit check. + +## `Carrier:HW678_2x22_Provisional` + +Component/top view: antenna up, USB connectors down. Origin is the top-left header +centre (pad 1), **not a PCB corner**. + +- Left row: pads 1 through 22, top to bottom, X=0. +- Right row: pads 23 through 44, top to bottom, X=25.40. +- Y=0 through 53.34 in 2.54 mm increments for each row (21 intervals). +- User breadboard fit verifies nominal 2.54 mm pitch and 25.40 mm row spacing; + these supersede the earlier raw caliper dimensions in README. +- Numbering follows the project's explicit convention, not a generic dual-row + connector's alternating or counterclockwise numbering. Physical numbers do + **not** establish GPIO, supply, or ground assignments. +- Only pads and annotation text are present. **No PCB outline, antenna keepout, + courtyard, USB envelope, mounting holes, or 3D model is guessed.** Text positions + are annotations, not dimensional evidence. Outline registration, antenna extent, + connector offsets/overhang, and assembly height remain unknown. + +## Validation and release gates + +Validation performed with KiCad 10.0.6 `pcbnew.FootprintLoad`: both footprints +parsed successfully. Assertions passed for pad counts, all numbered pad positions, +pad shapes/types/sizes/drills, OLED NPTH positions and diameters, both OLED `F.Fab` +rectangle bounds, and absence of courtyards, `Edge.Cuts`, and keepout zones. +HW678 was also checked to contain no graphical shapes. The local Python binding +emitted three startup `PROPERTY_ENUM` assertions (also seen on a version-only +import); these did not prevent loading or the checks from passing. + +Repeat the retained footprint regression checks from the repository root with: + +```sh +/usr/bin/python3 -B hardware/PCB/validate_footprints.py +``` + +This requires the system Python with KiCad's `pcbnew` binding. It checks the +native-loaded pad counts, coordinates, pad types, sizes, drills and geometry. Parsing is +not DRC, electrical verification, connector fit verification, or fabrication approval. +Print both footprints at 1:1 and check the real assemblies, especially HW678 row +numbering/orientation. Before layout release, select and verify connectors, map +HW678 pins from reliable board evidence, and establish module envelopes, +antenna restrictions, USB access, mounting hardware, and courtyards. diff --git a/hardware/PCB/fp-lib-table b/hardware/PCB/fp-lib-table new file mode 100644 index 0000000..292295c --- /dev/null +++ b/hardware/PCB/fp-lib-table @@ -0,0 +1,6 @@ +(fp_lib_table (version 7) + (lib (name "Carrier")(type "KiCad")(uri "${KIPRJMOD}/Carrier.pretty")(options "")(descr "Provisional module carrier footprints; see footprint-notes.md")) + (lib (name "Button_Switch_THT")(type "KiCad")(uri "${KICAD10_FOOTPRINT_DIR}/Button_Switch_THT.pretty")(options "")(descr "KiCad standard THT switches")) + (lib (name "Resistor_THT")(type "KiCad")(uri "${KICAD10_FOOTPRINT_DIR}/Resistor_THT.pretty")(options "")(descr "KiCad standard axial resistors")) + (lib (name "MountingHole")(type "KiCad")(uri "${KICAD10_FOOTPRINT_DIR}/MountingHole.pretty")(options "")(descr "KiCad standard mounting holes")) +) diff --git a/hardware/PCB/generate_pcb_draft.py b/hardware/PCB/generate_pcb_draft.py new file mode 100644 index 0000000..df8649f --- /dev/null +++ b/hardware/PCB/generate_pcb_draft.py @@ -0,0 +1,221 @@ +#!/usr/bin/env python3 +"""Create the compact placement draft from a fresh KiCad XML netlist. + +Requires system Python + pcbnew. Refuses to overwrite an existing PCB unless +--overwrite is explicit. This is a draft generator, not a manufacturing tool. +Does not modify the schematic or footprint libraries. KiCad SaveBoard also saves +PCB design settings into the project; close the project before regeneration. +""" +import argparse +import json +from pathlib import Path +import re +import subprocess +import xml.etree.ElementTree as ET +import pcbnew as p + +ROOT = Path(__file__).resolve().parent +PCB = ROOT / "serial-carrier.kicad_pcb" +LIBS = Path("/usr/share/kicad/footprints") +ORIGIN = (100, 100) +OUTLINE = [(0,0), (82,0), (82,80), (36,80), (36,61), (0,61)] +PLACEMENT = { + "U1": ("Carrier:HW678_2x22_Provisional", 8, 4), + "U2": ("Carrier:MAX3243_Reference_Provisional", 43, 30), + "DS1": ("Carrier:OLED_26mm_I2C_Provisional", 43, 36), + "R1": ("Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal", 43, 34), + "R2": ("Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal", 54, 34), + "R3": ("Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal", 65, 34), + "SW1": ("Button_Switch_THT:SW_TH_Tactile_Omron_B3F-100x", 43, 68), + "SW2": ("Button_Switch_THT:SW_TH_Tactile_Omron_B3F-100x", 55, 68), + "SW3": ("Button_Switch_THT:SW_TH_Tactile_Omron_B3F-100x", 67, 68), +} +MOUNTS = [(3.5,3.5), (3.5,56), (78,4), (78,76)] +# Deliberate allocation, NOT a measured antenna envelope or an RF guarantee. +RF_RESERVE = [(10,0), (31,0), (31,13), (10,13)] + +def mm(v): + return p.FromMM(v) + +def xy(x,y): + return p.VECTOR2I(mm(x+ORIGIN[0]), mm(y+ORIGIN[1])) + +def text(board, value, x, y, layer=p.F_SilkS, size=1): + item = p.PCB_TEXT(board) + item.SetText(value) + item.SetPosition(xy(x,y)) + item.SetLayer(layer) + item.SetTextSize(p.VECTOR2I(mm(size),mm(size))) + item.SetTextThickness(mm(0.15)) + board.Add(item) + return item + +def polygon(zone, points): + poly=zone.Outline() + poly.NewOutline() + for x,y in points: + pt=xy(x,y) + poly.Append(pt.x,pt.y) + +def load(lib_id): + lib,name=lib_id.split(":",1) + folder=ROOT / "Carrier.pretty" if lib=="Carrier" else LIBS / (lib+".pretty") + fp=p.FootprintLoad(str(folder),name) + if fp is None: + raise RuntimeError("Cannot load "+lib_id) + fp.SetFPIDAsString(lib_id) + return fp + +def quiet_footprint(fp): + # Retain all mechanical geometry, but replace sprawling research annotation + # text with concise board annotations. Libraries are never modified. + for graphic in list(fp.GraphicalItems()): + if isinstance(graphic,p.PCB_TEXT): + fp.Remove(graphic) + fp.Value().SetVisible(False) + fp.Reference().SetTextSize(p.VECTOR2I(mm(1),mm(1))) + fp.Reference().SetTextThickness(mm(0.15)) + fp.Reference().SetLayer(p.F_SilkS) + + +def copy_schematic_fields(fp, component): + for field in component.findall("fields/field"): + name=field.get("name") + if name in ("Reference", "Value", "Footprint"): + continue + fp.SetField(name, field.text or "") + fp.GetField(name).SetVisible(False) + + +def configure_draft_netclasses(): + # SaveBoard creates the project defaults. Align future interactive routing + # with the draft's physical minimum widths and its explicit power routing. + path=ROOT/"serial-carrier.kicad_pro" + project=json.loads(path.read_text()) + settings=project["net_settings"] + default=next(c for c in settings["classes"] if c["name"]=="Default") + default.update(clearance=0.25, track_width=0.25, via_diameter=0.7, via_drill=0.3) + power=dict(default, name="Power", priority=0, track_width=0.5, diff_pair_width=0.25) + settings["classes"]=[c for c in settings["classes"] if c["name"]!="Power"]+[power] + patterns=[v for v in settings.get("netclass_patterns",[]) if v["pattern"] not in ("/+3V3","/GND")] + settings["netclass_patterns"]=patterns+[{"netclass":"Power","pattern":name} for name in ("/+3V3","/GND")] + path.write_text(json.dumps(project,indent=2)+"\n") + + +def main(): + parser=argparse.ArgumentParser(description=__doc__) + parser.add_argument("--overwrite",action="store_true") + args=parser.parse_args() + if PCB.exists() and not args.overwrite: + parser.error("PCB exists; preserve manual edits or explicitly use --overwrite") + if any(ROOT.glob("~serial-carrier.*.lck")): + parser.error("Project is open in KiCad; close it before regenerating PCB/settings") + netfile=ROOT / "validation/pcb-source-netlist.xml" + subprocess.run(["kicad-cli","sch","export","netlist","--format","kicadxml","-o",str(netfile),str(ROOT/"serial-carrier.kicad_sch")],check=True) + source=ET.parse(netfile).getroot() + components={c.get("ref"):c for c in source.findall("components/comp")} + assert set(components)==set(PLACEMENT), "Schematic component set changed; review layout" + schematic=ROOT.joinpath("serial-carrier.kicad_sch").read_text() + root_uuid=re.search(r'\(uuid "?([a-f0-9-]{36})"?\)',schematic).group(1) + board=p.BOARD() + board.SetCopperLayerCount(2) + settings=board.GetDesignSettings() + settings.SetBoardThickness(mm(1.6)) + settings.m_MinClearance=mm(0.25) + settings.m_CopperEdgeClearance=mm(0.5) + settings.m_HoleClearance=mm(0.25) + settings.m_TrackMinWidth=mm(0.25) + settings.m_ViasMinSize=mm(0.7) + # SaveBoard persists these proposed draft rules into the project settings. + title=board.GetTitleBlock() + title.SetTitle("Serial Swiss Army Knife - 82x80 mm carrier draft") + title.SetRevision("A0 DRAFT") + title.SetComment(0,"NOT FOR FABRICATION - male module / USB / antenna geometry unverified") + pad_nets={} + for source_net in source.findall("nets/net"): + net=p.NETINFO_ITEM(board,source_net.get("name")) + board.Add(net) + for node in source_net.findall("node"): + pad_nets[node.get("ref"),node.get("pin")]=(net,node) + for ref,(lib_id,x,y) in PLACEMENT.items(): + comp=components[ref] + if ref != "U2": + assert comp.findtext("footprint")==lib_id,(ref,"Schematic footprint changed") + fp=load(lib_id) + fp.SetReference(ref) + fp.SetValue(comp.findtext("value")) + path=p.KIID_PATH() + path.push_back(p.KIID(root_uuid)) + path.push_back(p.KIID(comp.findtext("tstamps"))) + fp.SetPath(path) + fp.SetSheetfile("serial-carrier.kicad_sch") + fp.SetSheetname("serial-carrier") + fp.SetPosition(xy(x,y)) + board.Add(fp) + quiet_footprint(fp) + copy_schematic_fields(fp,comp) + if ref=="U1": + fp.Reference().SetPosition(xy(20.7,25)) + elif ref=="U2": + fp.Reference().SetPosition(xy(56.97,18)) + elif ref=="DS1": + fp.Reference().SetPosition(xy(56,49)) + elif ref.startswith("SW"): + fp.Reference().SetPosition(xy(x+3.25,y-2)) + else: + fp.Reference().SetLayer(p.F_Fab) + fp.Reference().SetPosition(xy(x+3.81,y-1.6)) + for pad in fp.Pads(): + key=ref,pad.GetNumber() + if pad.GetNumber(): + net,node=pad_nets[key] + pad.SetNet(net) + pad.SetPinFunction(node.get("pinfunction", "")) + pad.SetPinType(node.get("pintype", "passive")) + for i,(x,y) in enumerate(MOUNTS,1): + fp=load("MountingHole:MountingHole_3.2mm_M3") + fp.SetReference("H"+str(i)) + fp.SetValue("M3 mounting proposal / 3.2mm") + fp.SetBoardOnly(True) + fp.SetExcludedFromBOM(True) + fp.SetExcludedFromPosFiles(True) + fp.SetPosition(xy(x,y)) + board.Add(fp) + quiet_footprint(fp) + fp.Reference().SetVisible(False) + for a,b in zip(OUTLINE,OUTLINE[1:]+OUTLINE[:1]): + edge=p.PCB_SHAPE(board) + edge.SetShape(p.SHAPE_T_SEGMENT) + edge.SetStart(xy(*a)); edge.SetEnd(xy(*b)) + edge.SetLayer(p.Edge_Cuts); edge.SetWidth(mm(0.05)) + board.Add(edge) + reserve=p.ZONE(board) + reserve.SetIsRuleArea(True) + layers=p.LSET(); layers.AddLayer(p.F_Cu); layers.AddLayer(p.B_Cu) + reserve.SetLayerSet(layers) + reserve.SetZoneName("PROVISIONAL RF RESERVE - verify actual antenna clearance") + reserve.SetDoNotAllowTracks(True); reserve.SetDoNotAllowVias(True) + reserve.SetDoNotAllowZoneFills(True); reserve.SetDoNotAllowPads(True) + reserve.SetDoNotAllowFootprints(False) # the module itself spans this region + polygon(reserve,RF_RESERVE) + board.Add(reserve) + text(board,"RF RESERVE",20.5,7,p.Dwgs_User,1.2) + text(board,"VERIFY ANTENNA",20.5,10,p.Dwgs_User,1) + text(board,"ESP32 HW678",20.7,29) + text(board,"USB ACCESS - VERIFY",18,64,p.Dwgs_User,1) + text(board,"DE-9 OUT / VERIFY MALE",56.97,1.5,p.Dwgs_User,1) + text(board,"MAX3243 REF",56.97,21) + text(board,"26mm OLED",56,52) + for label,x in zip(("BACK","SELECT","NEXT"),(46.25,58.25,70.25)): + text(board,label,x,75, size=0.9) + text(board,"DRAFT - NOT FOR FAB",56,78,size=0.9) + text(board,"82 x 80 mm / 2 copper layers",41,-5,p.Dwgs_User,1.5) + text(board,"Carrier envelope only; module overhang and connector clearance not qualified",41,-2.5,p.Dwgs_User,0.9) + board.BuildConnectivity() + p.SaveBoard(str(PCB),board) + configure_draft_netclasses() + print("Created",PCB,"with 9 circuit footprints, 4 proposed M3 mounts, 2 copper layers.") + print("Placement draft only. Board-only U2 footprint is a female-CAD reference, not male qualification.") + +if __name__=="__main__": + main() diff --git a/hardware/PCB/generate_schematic.py b/hardware/PCB/generate_schematic.py new file mode 100644 index 0000000..85f5190 --- /dev/null +++ b/hardware/PCB/generate_schematic.py @@ -0,0 +1,167 @@ +#!/usr/bin/env python3 +"""Generate the initial native KiCad carrier schematic (Python stdlib only). + +Explicit bootstrap/regeneration tool: overwrites the generated schematic, symbol +library and library tables. Do not run over subsequent manual KiCad edits without +reviewing/backing them up. It does not regenerate footprints or the fit template. +""" +import json +from pathlib import Path +import uuid + +ROOT = Path(__file__).resolve().parent +PROJECT = "serial-carrier" +NS = uuid.UUID("b6f75dd1-a843-42f2-9067-57c995968145") + +def uid(key): + return str(uuid.uuid5(NS, key)) + +def q(value): + return json.dumps(str(value), ensure_ascii=False) + +def n(value): + return f"{value:.4f}".rstrip("0").rstrip(".") if value else "0" + +def effects(size=1.27, extra=""): + return f"(effects (font (size {size} {size})) {extra})" + +def prop(name, value, x=0, y=0, hidden=False): + return f'(property {q(name)} {q(value)} (at {n(x)} {n(y)} 0) {effects(extra="(hide yes)" if hidden else "")})' + +# Physical module numbering is a project convention, not ESP32 GPIO numbering: +# component side, antenna up / USB down; left row 1..22, right row 23..44. +left = ["3V3", "3V3", "EN", "GPIO4", "GPIO5", "GPIO6", "GPIO7", "GPIO15", "GPIO16", "GPIO17", "GPIO18", "GPIO8", "GPIO3", "GPIO46", "GPIO9", "GPIO10", "GPIO11", "GPIO12", "GPIO13", "GPIO14", "5V", "GND"] +right = ["GND", "GPIO43", "GPIO44", "GPIO1", "GPIO2", "GPIO42", "GPIO41", "GPIO40", "GPIO39", "GPIO38", "GPIO37", "GPIO36", "GPIO35", "GPIO0", "GPIO45", "GPIO48", "GPIO47", "GPIO21", "GPIO20", "GPIO19", "GND", "GND"] +GPIO_NET = {4:"RS_DCD",5:"RS_DSR",6:"RS_RI",7:"RS_DTR",8:"RS_VALID",9:"RS_OFF_N",10:"BTN_PREVIOUS",11:"OLED_SDA",12:"OLED_SCL",13:"BTN_SELECT",14:"BTN_NEXT",15:"RS_RTS",16:"RS_CTS",17:"RS_TX",18:"RS_RX"} +OUTPUTS = {7, 12, 15, 17} +INPUTS = {4, 5, 6, 8, 10, 13, 14, 16, 18} + +def gpio_type(name): + if not name.startswith("GPIO"): + return "input" if name == "EN" else "passive" + number = int(name[4:]) + if number == 9: + # Model the programmable MCU pad, not a discrete open-collector device. + # The required firmware open-drain mode and module pull-up are noted on sheet. + return "bidirectional" + return "output" if number in OUTPUTS else "input" if number in INPUTS else "bidirectional" + +# Pin tuples: physical number, name, electrical type, local X, local Y, angle. +MCU = [] +for side, names in enumerate((left, right)): + for index, name in enumerate(names): + number = index + 1 + side * 22 + kind = "power_out" if number in (1, 22) else gpio_type(name) + MCU.append((str(number), name, kind, -22.86 if side == 0 else 22.86, 26.67-index*2.54, 0 if side == 0 else 180)) + +# Published Adafruit 5988 CAD reference; male 6253 correspondence is provisional. +RS_NAMES = ["Vin", "GND", "DCD", "RX", "TX", "DTR", "DSR", "RTS", "CTS", "RI", "VLD", "OFF_N"] +RS = [(str(i+1), name, "power_in" if i < 2 else "input" if name in ("TX","DTR","RTS","OFF_N") else "output", -20.32, 13.97-i*2.54, 0) for i,name in enumerate(RS_NAMES)] +OLED = [(str(i+1),name,kind,-15.24,3.81-i*2.54,0) for i,(name,kind) in enumerate((("GND","power_in"),("VCC","power_in"),("SCL","input"),("SDA","bidirectional")))] +TWO = [("1","~","passive",-5.08,0,0),("2","~","passive",5.08,0,180)] + +SPECS = { + "HW678_N16R8": (MCU, 17.78, 29.21, "U", "Carrier:HW678_2x22_Provisional", "HW-678 V0.0.0 / N16R8 carrier interface; project numbering; onboard USB/regulator retained"), + "MAX3243_Module_Reference": (RS, 15.24, 17.78, "U", "", "Adafruit male 6253 intended; physical numbering from published female 5988 CAD, VERIFY MALE"), + "OLED_I2C_26mm": (OLED, 10.16, 7.62, "DS", "Carrier:OLED_26mm_I2C_Provisional", "User fit-verified 26 mm OLED; front/top header GND VCC SCL SDA"), + "SW_NO": (TWO, 2.54, 2.54, "SW", "Button_Switch_THT:SW_TH_Tactile_Omron_B3F-100x", "Normally open contact; footprint duplicates pads 1 and 2 for internally common terminal pairs"), + "R": (TWO, 2.54, 1.016, "R", "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal", "Resistor, axial DIN0207 footprint; exact MPN pending") +} + +def symbol_definition(name, embedded=False): + pins, halfwidth, halfheight, ref, footprint, description = SPECS[name] + out = [f'(symbol {q("Carrier:"+name if embedded else name)} (pin_names (offset 0.762)) (in_bom yes) (on_board yes)', + prop("Reference", ref, 0, halfheight+5.08), prop("Value", name, 0, halfheight+2.54), + prop("Footprint", footprint, hidden=True), prop("Datasheet", "", hidden=True), prop("Description",description,hidden=True)] + if name == "SW_NO": + shape = '(polyline (pts (xy -2.54 0) (xy 2.54 1.524)) (stroke (width 0.254) (type default)) (fill (type none)))' + shape += ''.join(f'(circle (center {x} 0) (radius 0.35) (stroke (width 0.1524) (type default)) (fill (type none)))' for x in (-2.54,2.54)) + else: + shape = f'(rectangle (start {-halfwidth} {halfheight}) (end {halfwidth} {-halfheight}) (stroke (width 0.254) (type default)) (fill (type background)))' + out.append(f'(symbol {q(name+"_0_1")} {shape})') + out.append(f'(symbol {q(name+"_1_1")}') + for number,label,kind,x,y,angle in pins: + length = abs(x)-halfwidth + out.append(f'(pin {kind} line (at {n(x)} {n(y)} {angle}) (length {n(length)}) (name {q(label)} {effects(1.016)}) (number {q(number)} {effects(1.016)}))') + out.extend([')', ')']) + return '\n'.join(out) + +ROOT.joinpath("Carrier.kicad_sym").write_text('(kicad_symbol_lib (version 20231120) (generator "kicad_symbol_editor")\n'+'\n'.join(symbol_definition(name) for name in SPECS)+'\n)\n') +ROOT.joinpath("sym-lib-table").write_text('(sym_lib_table (version 7)\n (lib (name "Carrier")(type "KiCad")(uri "${KIPRJMOD}/Carrier.kicad_sym")(options "")(descr "Project-local module interfaces"))\n)\n') +ROOT.joinpath("fp-lib-table").write_text('(fp_lib_table (version 7)\n (lib (name "Carrier")(type "KiCad")(uri "${KIPRJMOD}/Carrier.pretty")(options "")(descr "Provisional module carrier footprints; see footprint-notes.md"))\n (lib (name "Button_Switch_THT")(type "KiCad")(uri "${KICAD10_FOOTPRINT_DIR}/Button_Switch_THT.pretty")(options "")(descr "KiCad standard THT switches"))\n (lib (name "Resistor_THT")(type "KiCad")(uri "${KICAD10_FOOTPRINT_DIR}/Resistor_THT.pretty")(options "")(descr "KiCad standard axial resistors"))\n (lib (name "MountingHole")(type "KiCad")(uri "${KICAD10_FOOTPRINT_DIR}/MountingHole.pretty")(options "")(descr "KiCad standard mounting holes"))\n)\n') +# Preserve project settings on regeneration. +project_file = ROOT / (PROJECT + ".kicad_pro") +if not project_file.exists(): + project_file.write_text(json.dumps({"meta":{"filename":project_file.name,"version":3}},indent=2)+"\n") + +root_uuid = uid("root") +items = [f'(kicad_sch (version 20250114) (generator "eeschema") (uuid {q(root_uuid)}) (paper "A3")', + '(title_block (title "ESP32 Serial Swiss Army Knife - Module Carrier") (date "2026-09-20") (rev "A0 DRAFT") (comment 1 "Not fabrication-ready: provisional module footprints and male RS-232 mapping"))', + '(lib_symbols '+'\n'.join(symbol_definition(name,True) for name in SPECS)+')'] +expected = {} + +def wire(x1,y1,x2,y2,key): + items.append(f'(wire (pts (xy {n(x1)} {n(y1)}) (xy {n(x2)} {n(y2)})) (stroke (width 0) (type default)) (uuid {q(uid("wire:"+key))}))') + +def label(net,x,y,key): + items.append(f'(label {q(net)} (at {n(x)} {n(y)} 0) {effects(1.016,"(justify left bottom)")} (uuid {q(uid("label:"+key))}))') + +def note(text,x,y,size=1.27): + items.append(f'(text {q(text)} (at {n(x)} {n(y)} 0) {effects(size,"(justify left top)")} (uuid {q(uid("text:"+text))}))') + +def place(name,ref,value,x,y,nets,extra=None): + pins,hw,hh,_,footprint,description = SPECS[name] + instance = [f'(symbol (lib_id {q("Carrier:"+name)}) (at {n(x)} {n(y)} 0) (unit 1) (in_bom yes) (on_board yes) (dnp no) (uuid {q(uid(ref))})', + prop("Reference",ref,x,y-hh-5.08),prop("Value",value,x,y-hh-2.54),prop("Footprint",footprint,x,y,True),prop("Datasheet","",x,y,True)] + for k,v in (extra or {}).items(): + instance.append(prop(k,v,x,y,True)) + instance.extend(f'(pin {q(p[0])} (uuid {q(uid(ref+":"+p[0]))}))' for p in pins) + instance.append(f'(instances (project {q(PROJECT)} (path {q("/"+root_uuid)} (reference {q(ref)}) (unit 1)))))') + items.append('\n'.join(instance)) + for number,_,_,px,py,angle in pins: + ax,ay=x+px,y-py + net=nets.get(number) + key=ref+":"+number + if net is None: + items.append(f'(no_connect (at {n(ax)} {n(ay)}) (uuid {q(uid("nc:"+key))}))') + else: + end=ax-12.7 if angle==0 else ax+12.7 + wire(ax,ay,end,ay,key) + label(net,end,ay,key) + expected.setdefault(net,[]).append([ref,number]) + +mcu_nets={} +for number,name,*_ in MCU: + if name == "3V3": + mcu_nets[number]="+3V3" + elif name == "GND": + mcu_nets[number]="GND" + elif name.startswith("GPIO") and int(name[4:]) in GPIO_NET: + mcu_nets[number]=GPIO_NET[int(name[4:])] +place("HW678_N16R8","U1","HW678 / S3-N16R8",95.25,109.22,mcu_nets,{"Status":"Header geometry nominal; outline/antenna clearance pending","Pin_numbering":"Left 1-22; right 23-44; both top-to-bottom, antenna up"}) +rs_nets=dict(zip(map(str,range(1,13)),["+3V3","GND","RS_DCD","RS_RX","RS_TX","RS_DTR","RS_DSR","RS_RTS","RS_CTS","RS_RI","RS_VALID","RS_OFF_N"])) +place("MAX3243_Module_Reference","U2","Adafruit MAX3243 / male 6253",228.6,96.52,rs_nets,{"Status":"VERIFY male header numbering; footprint intentionally unassigned","Datasheet_source":"adafruit-research.md; reference female 5988 CAD"}) +place("OLED_I2C_26mm","DS1","128x64 I2C OLED / 0x3C",228.6,152.4,{"1":"GND","2":"+3V3","3":"OLED_SCL","4":"OLED_SDA"},{"Status":"Module outline/header/display user fit-verified; pad/drill fit provisional"}) +for index,(net,function) in enumerate((("BTN_PREVIOUS","Previous / back"),("BTN_SELECT","Select / confirm"),("BTN_NEXT","Next")),1): + y=88.9+(index-1)*35.56 + place("R",f"R{index}","2.2k 1%",327.66,y,{"1":"+3V3","2":net},{"Rating":"At least 0.125 W; exact resistor MPN pending"}) + place("SW_NO",f"SW{index}","B3F-1000",327.66,y+15.24,{"1":net,"2":"GND"},{"Manufacturer":"Omron","MPN":"B3F-1000","Function":function,"Procurement":"Live stock not verified"}) + note(function,302.26,y+21.59,1.016) + +note("MODULE CARRIER - INITIAL SCHEMATIC",15.24,15.24,2.54) +note("Native KiCad 10 schematic. Named wire labels join matching nets on this sheet.\nRead hardware/PCB/README.md before layout or fabrication.",15.24,24.13) +note("U1: complete development board",53.34,57.15,1.778) +note("Antenna up / USB down: left row 1-22, right row 23-44.\nNC marks mean unused on carrier, not unused inside module.",53.34,64.77,1.016) +note("U2: complete RS-232 breakout",177.8,57.15,1.778) +note("Male 6253 selected. Numbers from published 5988 female CAD.\nVERIFY male header before routing; no footprint assigned.\nDE-9 and charge pump are already on the module.",177.8,64.77,1.016) +note("Controls: active-low, firmware-debounced",292.1,57.15,1.778) +note("External 2.2k pull-ups: ~1.5 mA pressed at 3.3 V.\nChosen for B3F-1000 rated contact load; internal\npull-ups may remain enabled. Exact resistor MPN pending.",292.1,64.77,1.016) +note("DS1: front view GND / VCC / SCL / SDA",177.8,128.27,1.524) +note("Power at 3.3 V only. Verify on-module I2C pull-ups;\nexternal values intentionally not guessed.",177.8,165.1,1.016) +note("POWER / RECOVERY\nPower only through U1's existing USB ports. No carrier 5 V input.\nU1 regulator supplies +3V3; GND pins are common on the module.\nPin 1 +3V3 and pin 22 GND model the onboard supply for ERC.\nGPIO19/20 native USB and GPIO43/44 UART0 remain onboard.\nVerify USB power isolation before attaching two powered hosts.\nKeep both USB connectors and reset/boot buttons accessible.",15.24,185.42) +note("RS-232 / ELECTRICAL LIMITS\nTX/RX and modem labels are at the ESP32 logic side.\nOFF_N is active low; GPIO9 must remain open-drain.\nBreakout provides its OFF pull-up. No galvanic isolation.\nNo carrier connection to raw RS-232 voltages.\nCarrier GND, USB GND and RS-232 signal ground are common.\nNever power OLED or MAX3243 logic from 5 V.",152.4,185.42) +note("BEFORE PCB RELEASE\nVerify male breakout pin order/footprint.\nConfirm header/socket finished-hole requirements.\nComplete module courtyards and antenna clearance.\nVerify 3.3 V budget, OLED pull-ups and USB power path.\nChoose mounting hardware and confirm button stock.\nERC is not hardware or fabrication approval.",292.1,185.42) +items.append(')') +ROOT.joinpath(PROJECT+".kicad_sch").write_text('\n'.join(items)+'\n') +ROOT.joinpath("validation/expected-nets.json").write_text(json.dumps(expected,indent=2,sort_keys=True)+'\n') +print("Generated native KiCad schematic, project-local symbol library and tables.") diff --git a/hardware/PCB/oled-fit-check.svg b/hardware/PCB/oled-fit-check.svg new file mode 100644 index 0000000..1af734d --- /dev/null +++ b/hardware/PCB/oled-fit-check.svg @@ -0,0 +1,37 @@ + + OLED module mechanical fit check — front view + 26 mm square PCB, four 2 mm mounting holes at 1.75 mm edge offsets. Centred four-pin header at 2.54 mm pitch, 1.50 mm from top edge. Display outline at (1, 4.5), measuring 24.5 × 16.5 mm. Header crosses indicate centres only, not drill sizes. + + OLED mechanical fit check — front view + Print at 100%; disable fit-to-page. + Verify the scale below before use. + + + + + + + + + + + GND + VCC + SCL + SDA + Dashed: display outline + 24.5 × 16.5 mm + 26 × 26 mm PCB + Holes: Ø2 mm + Hole spacing: 22.50 mm + + + + + + + 20 mm scale + Header crosses mark pin centres, not drill sizes. + Mechanical reference only — not a fabrication file. + + diff --git a/hardware/PCB/pcb-draft-notes.md b/hardware/PCB/pcb-draft-notes.md new file mode 100644 index 0000000..e7f91c0 --- /dev/null +++ b/hardware/PCB/pcb-draft-notes.md @@ -0,0 +1,173 @@ +# Compact two-layer PCB — A0 draft + +Open **`serial-carrier.kicad_pcb`** in KiCad 10. The routed board belongs to the +existing `serial-carrier.kicad_pro` / `.kicad_sch` project. **Not for fabrication.** +No Gerbers, production drills or manufacturing archive were generated. + +## Size and placement + +- **Carrier bounding dimensions: 82 × 80 mm**, within the requested 100 × 100 mm. +- **Two copper layers**, F.Cu and B.Cu. All components mount on the front. +- Proposed **1.6 mm** carrier thickness; fabrication stackup/process not selected. +- Stepped outline: a **36 × 19 mm lower-left cutaway** leaves cable space below + the ESP32 while the OLED/buttons occupy the deeper right-hand section. +- Module and mating-plug overhangs are not included in the carrier dimensions. + The final complete assembly/enclosure envelope still needs measurement. + +Coordinates in the following table are local millimetres from the carrier's +upper-left corner, X right/Y down, viewed from the component side. In the KiCad +file add (100, 100) mm to obtain absolute board coordinates. All footprints are +unrotated; their origins are defined in the footprint notes, not necessarily +component body corners. + +| Reference | Local origin (X, Y) | Placement | +|---|---|---| +| U1 | (8, 4) | ESP32 left header pin 1; antenna toward upper edge, USB toward cutaway | +| U2 | (43, 30) | MAX3243 header pin 1; DE-9 toward upper edge | +| DS1 | (43, 36) | OLED module upper-left PCB corner; display faces up | +| R1 / R2 / R3 | (43 / 54 / 65, 34) | Axial pull-ups in the gap between RS-232 and OLED | +| SW1 / SW2 / SW3 | (43 / 55 / 67, 68) | Back, select, next below display; switch pad 1 origins | +| H1 | (3.5, 3.5) | Proposed case mounting hole | +| H2 | (3.5, 56) | Proposed case mounting hole | +| H3 | (78, 4) | Proposed case mounting hole | +| H4 | (78, 76) | Proposed case mounting hole | + +Outline vertices: (0,0), (82,0), (82,80), (36,80), (36,61), (0,61), closed. +The board area is **58.76 cm²**; its bounding rectangle is 65.6 cm². + +H1–H4 are proposed **Ø3.2 mm NPTH M3 clearance holes**, not a previously agreed +case specification. They are marked board-only and excluded from the electrical +BOM. The OLED and RS-232 module mounting holes are additional, separate holes. +Screw heads, spacers, heat-set inserts, tool access and underside lead clearance +must be checked against the final case and assembly heights. No insert dimensions +or module stand-off heights are assumed. + +## Routing and electrical status + +The PCB contains actual copper, not just ratsnest placement: + +- All **38 required physical-pad spanning connections** across **17 connected + nets** routed, including both duplicated pads of each switch contact. +- **569 segments**, signal width **0.25 mm**, 3.3 V and GND width **0.50 mm**. +- **20 through vias**, **0.70 mm copper / 0.30 mm drill**. +- **No copper pours**; ground is explicitly routed. This is an initial routing + solution, not a reviewed return-current/EMI or power-integrity design. +- Proposed minimum different-net clearance **0.25 mm** and copper-edge clearance + **0.50 mm**. These are selected draft design rules, not fabrication qualification. +- Project netclasses align interactive routing defaults with the draft: Default + uses 0.25 mm tracks / 0.25 mm clearance, while Power matches `/+3V3` and `/GND` + with 0.50 mm tracks. Both use 0.70 / 0.30 mm vias. +- Schematic pad-net assignments, component values and UUID linkage are retained. + U1's intentionally unused GPIO/USB/UART0/5 V header pads remain unused. + +The bounded draft router prioritizes connectivity and conservative geometric +clearance, not optimal trace topology. Do not treat DRC passage as evidence of +current-carrying capacity, supply stability, I²C signal quality or EMC compliance. + +## Explicit provisional mechanical choices + +### ESP32 and RF + +A two-layer **no-tracks/no-vias/no-pads/no-zone-fill rule area** reserves local +X=10…31 mm, Y=0…13 mm toward the antenna. This is a deliberate carrier design +allocation, **not a measured antenna envelope or a manufacturer RF keepout**. +The module itself may span the rule area; footprint placement is not forbidden. +No carrier copper enters the reserve, but copper runs close to its boundary. + +U1's exact PCB/antenna/USB offsets are still unmeasured. The intended antenna +overhang and USB access must be checked with the actual board and a printed +placement template. Move U1, change the edge or enlarge the reserve if required. +Missing RF clearance cannot be signed off from the current footprint alone. + +### RS-232 + +U2 uses the new **`Carrier:MAX3243_Reference_Provisional`** footprint **on the PCB +only**. Its bare-module outline/header/holes are adapted from published female +5988 CAD for the intended male 6253 module. The user reports identical dimensions, +but the male header map and assembled DE-9 envelope are still unverified. +See `rs232-footprint-notes.md` and its CC BY-SA attribution. + +The schematic footprint remains intentionally blank, preserving its caution +and avoiding edits to the schematic that was open in KiCad. Consequently there +is **one known schematic-parity warning**: U2 footprint differs from the empty +schematic assignment. This is not excluded/suppressed, and is not a net mismatch. +Once the male footprint is qualified, explicitly assign it in the schematic +before relying on Update PCB from Schematic to manage U2's footprint. + +### OLED and controls + +OLED geometry, including its display boundary, is the user-fit-verified geometry. +The module schematic/library files are unchanged. The new overall placement still +needs an assembly fit check: adjacent resistor bodies, module underside parts, +header/socket bodies, button actuation and finger/plunger clearance are not +represented by complete assembly courtyards. In particular the axial resistors +are tightly packed between the module outlines; confirm clearance and height. + +## Review outputs + +- `validation/pcb-draft.svg` / `pcb-draft.png`: combined copper/outline/fab review. +- `validation/pcb-draft-3d.png`: KiCad render of the carrier and available standard + component models. **ESP32, OLED and RS-232 assembled module models are absent**; + the render is not an assembled-device or enclosure fit check. +- `pcb-placement-draft.pdf`: **1:1** front placement/pad/outline drawing. Print at + 100%, disable fit-to-page, and confirm the outer width is 82 mm before use. + It includes only known module outlines; no guessed U1 body or DE-9 envelope. + +## Validation and limits + +Run from the repository root with the system Python containing KiCad bindings: + +```sh +/usr/bin/python3 -B hardware/PCB/validate_pcb_draft.py +/usr/bin/python3 -B hardware/PCB/validation/pcb-routing-check.py +``` + +The first script exports a **fresh saved-schematic netlist** and checks the actual +PCB pad assignments, component linkage, dimensions, layer count, nominal thickness, +mounting holes, track/via sizes and KiCad DRC. It never rewrites the PCB or project. +It reports the single expected U2 parity warning explicitly, and fails on any +other parity issue, DRC violation or unconnected item. Reports are retained in +`validation/pcb-parity-drc.json` and `pcb-validation-summary.json`. + +The second independently checks continuous copper/hole/edge geometry and original +placement/net/UUID preservation against the initial unrouted snapshot. It needs +locally installed NumPy and Shapely in addition to pcbnew. It is not a substitute +for current-schematic net validation and is specific to this initial layout. + +Results with KiCad **10.0.6**: + +- **0 physical DRC errors/warnings; 0 unconnected items.** +- All saved-schematic pad nets match the PCB; **1 expected U2 footprint parity warning**. +- Independent minimum different-net/copper-to-NPTH gap **0.275 mm**; minimum + copper/NPTH-to-board-edge gap **0.525 mm**. +- All 9 electrical footprints, 4 board-only mounts, outline and RF area retained. +- Startup `PROPERTY_ENUM` assertions from the local pcbnew binding are still + emitted, but the checks complete successfully. + +DRC uses the existing default ignored checks: `missing_courtyard`, +`track_not_centered_on_via`, `tuning_profile_track_geometries`, +`footprint_filters_mismatch`, `footprint_type_mismatch`. No new exclusions were +added to hide problems. **Missing module courtyards therefore remain an explicit +manual release gate**. The draft rules do not represent a chosen fabricator's +complete capability set. No electrical/hardware/fabrication tests were performed. + +## Regeneration and project settings + +Normal use is to **edit the native PCB in KiCad**, not regenerate it. The optional +`generate_pcb_draft.py` recreates the *unrouted* initial placement and discards +manual PCB work only with explicit `--overwrite`; it refuses an open-project lock. +KiCad's initial SaveBoard populated the previously minimal `.kicad_pro` with PCB +settings and draft clearance/width rules. The schematic was not modified. If the +project was already open, reopen it to load the saved PCB settings before review. + +`route_pcb_draft.py` requires NumPy and pcbnew. By default it never saves; replacing +existing tracks requires explicit `--route --overwrite --replace-routes`. Do not +run that over manual routing without a backup. It is a bounded initial-draft +router, **not** a general-purpose autorouter. See `validation/pcb-routing-summary.md` +for algorithm limits and commands. These scripts do not need downloaded packages +or services in the current environment and create no manufacturing outputs. + +Before fabrication: qualify all module pin maps/footprints and connectors, +complete assembly courtyards and RF/USB/DE-9 checks, review power/return paths, +verify the existing USB power circuit and OLED pull-ups, confirm procurement and +case hardware, rerun ERC/DRC, and perform an independent hardware design review. diff --git a/hardware/PCB/pcb-placement-draft.pdf b/hardware/PCB/pcb-placement-draft.pdf new file mode 100644 index 0000000000000000000000000000000000000000..9b08105b2c51c8d9f8ffede1ad2f510a3c188482 GIT binary patch literal 50997 zcmeFYbzGEP*Do#|(k0CxNY{`$bX6{?= z=Q$6*_w}6L`SbO|XRcXm?`yl(-fMl=T6^z#q9P&13}oR#ed6oqAArgQU<25_c!??? z0AN)xwKaFL0C0m@Y5-O#OKT@n2k_I{$jMZ~)Y#6%6d)vo>geQPYGi}z`hCSqu@s)S ze7xD`OB&Kc?daSNjF~zFN^0%4qXV1weZj6y4}pM)&QjW|v{%`ibHyL^nijqlG?b=U z@<&FE61^HR-J5Bqy_o8|oy^E+@u`jSp}oBlZ#dYWyq&l`i@H6bvJ>jW623WkTlbnO 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This is the same library that we use internally, and it is regularly updated. The newest version can always be found at <b>www.microBuilder.eu</b>. If you find this library useful, please feel free to purchase something from our online store. Please also note that all holes are optimised for metric drill bits!</p> + +<h3>Obligatory Warning</h3> +<p>While it probably goes without saying, there are no guarantees that the footprints or schematic symbols in this library are flawless, and we make no promises of fitness for production, prototyping or any other purpose. These libraries are provided for information puposes only, and are used at your own discretion. While we make every effort to produce accurate footprints, and many of the items found in this library have be proven in production, we can't make any promises of suitability for a specific purpose. If you do find any errors, though, please feel free to contact us at www.microbuilder.eu to let us know about it so that we can update the library accordingly!</p> + +<h3>License</h3> +<p>This work is placed in the public domain, and may be freely used for commercial and non-commercial work with the following conditions:</p> +<p>THIS SOFTWARE IS PROVIDED ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +</p> + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + +<b>Revision Level Field</b> - 40 mil<p> +Set version with global board attribute '>REV' + +>REV + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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The ids +of those online libraries will not be understood (or retained) +with this version. + + +Since Version 8.3, EAGLE supports URNs for individual library +assets (packages, symbols, and devices). The URNs of those assets +will not be understood (or retained) with this version. + + +Since Version 8.3, EAGLE supports the association of 3D packages +with devices in libraries, schematics, and board files. Those 3D +packages will not be understood (or retained) with this version. + + + diff --git a/hardware/PCB/reference/Adafruit RS-232 Full Pinout Level-Shifter Breakout.sch b/hardware/PCB/reference/Adafruit RS-232 Full Pinout Level-Shifter Breakout.sch new file mode 100644 index 0000000..fcaf010 --- /dev/null +++ b/hardware/PCB/reference/Adafruit RS-232 Full Pinout Level-Shifter Breakout.sch @@ -0,0 +1,2696 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<h2><b>microBuilder.eu</b> Eagle Footprint Library</h2> + +<p>Footprints for common components used in our projects and products. This is the same library that we use internally, and it is regularly updated. The newest version can always be found at <b>www.microBuilder.eu</b>. If you find this library useful, please feel free to purchase something from our online store. Please also note that all holes are optimised for metric drill bits!</p> + +<h3>Obligatory Warning</h3> +<p>While it probably goes without saying, there are no guarantees that the footprints or schematic symbols in this library are flawless, and we make no promises of fitness for production, prototyping or any other purpose. These libraries are provided for information puposes only, and are used at your own discretion. While we make every effort to produce accurate footprints, and many of the items found in this library have be proven in production, we can't make any promises of suitability for a specific purpose. If you do find any errors, though, please feel free to contact us at www.microbuilder.eu to let us know about it so that we can update the library accordingly!</p> + +<h3>License</h3> +<p>This work is placed in the public domain, and may be freely used for commercial and non-commercial work with the following conditions:</p> +<p>THIS SOFTWARE IS PROVIDED ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 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Courtesy Robert Starr (bobstarr.net)</p> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>SHEET +REV +TITLE +DRG +o +>DRAWING_NAME +N +DATE +>LAST_DATE_TIME +>YEAR +C +ISSUE +DRAWN +CHECKED +DATE +>COMPANY +FILE: +PAGE: +>DRAWN +>CHECKED +>DATE +>DRGNO +>REV + + + + +>NAME +>VALUE + + + + + + + +>VALUE + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + +<b>FRAME</b><p> +DIN A4, landscape with location and doc. field + + + + + + + + + + + + + +<p><b>Ceramic Capacitors</b></p> +<p>For new designs, use the packages preceded by an '_' character since they are more reliable:</p> +<p>The following footprints should be used on most boards:</p> +<ul> +<li><b>_0402</b> - Standard footprint for regular board layouts</li> +<li><b>_0603</b> - Standard footprint for regular board layouts</li> +<li><b>_0805</b> - Standard footprint for regular board layouts</li> +<li><b>_1206</b> - Standard footprint for regular board layouts</li> +</ul> +<p>For extremely tight-pitch boards where space is at a premium, the following 'micro-pitch' footprints can be used (smaller pads, no silkscreen outline, etc.):</p> +<ul> +<li><b>_0402MP</b> - Micro-pitch footprint for very dense/compact boards</li> +<li><b>_0603MP</b> - Micro-pitch footprint for very dense/compact boards</li> +<li><b>_0805MP</b> - Micro-pitch footprint for very dense/compact boards</li> +<li><b>_1206MP</b> - Micro-pitch footprint for very dense/compact boards</li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>GND</b> + + + + + + + + + + + + +<b>Mounting Hole</b> +<p>For #2 screws (0.086"/2.18mm width, 0.094"/2.4mm hole) use 2.5mm</p> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<p><b>Resistors</b></p> +<p>For new designs, use the packages preceded by an '_' character since they are more reliable:</p> +<p>The following footprints should be used on most boards:</p> +<ul> +<li><b>_0402</b> - Standard footprint for regular board layouts</li> +<li><b>_0603</b> - Standard footprint for regular board layouts</li> +<li><b>_0805</b> - Standard footprint for regular board layouts</li> +<li><b>_1206</b> - Standard footprint for regular board layouts</li> +</ul> +<p>For extremely tight-pitch boards where space is at a premium, the following 'micro-pitch' footprints can be used (smaller pads, no silkscreen outline, etc.):</p> +<ul> +<li><b>_0402MP</b> - Micro-pitch footprint for very dense/compact boards</li> +<li><b>_0603MP</b> - Micro-pitch footprint for very dense/compact boards</li> +<li><b>_0805MP</b> - Micro-pitch footprint for very dense/compact boards</li> +<li><b>_1206MP</b> - Micro-pitch footprint for very dense/compact boards</li> +</ul> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE + + + + + +<b>SUPPLY SYMBOL</b> + + + + + + + + + + + + + + +<b>Maxim Components</b><p> + +<author>Created by librarian@cadsoft.de</author> + + +<b>Shrink Small Outline Package</b><p> +package type SS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>Thin Shrink Small Outline Plastic 28</b><p> +MAX3223-MAX3243.pdf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>Small Outline Package</b><p> +MAX3221-MAX3243.pdf; SO28W + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE +>NAME + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Shrink Small Outline Package +package type SS + + + + + +Thin Shrink Small Outline Plastic 28 +MAX3223-MAX3243.pdf + + + + + +Small Outline Package +MAX3221-MAX3243.pdf; SO28W + + + + + + + +GND +VCC +>NAME + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>RS-232 Transceivers with AutoShutdown</b><p> +1µA Supply-Current, True +3V to +5.5V<br> +http://dbserv.maxim-ic.com/ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>SUB-D</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +1 +5 +9 +6 +2,54 +F09 + + + + + + + + + + + + + + + +SUB-D + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE +>NAME + + + + + + + + + + + + + + + +<b>SUB-D</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +For C2, see p.7 of DS (R1xCF) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Since Version 8.2, EAGLE supports online libraries. The ids +of those online libraries will not be understood (or retained) +with this version. + + +Since Version 8.3, EAGLE supports URNs for individual library +assets (packages, symbols, and devices). The URNs of those assets +will not be understood (or retained) with this version. + + +Since Version 8.3, EAGLE supports the association of 3D packages +with devices in libraries, schematics, and board files. Those 3D +packages will not be understood (or retained) with this version. + + + diff --git a/hardware/PCB/reference/README.md b/hardware/PCB/reference/README.md new file mode 100644 index 0000000..13208c7 --- /dev/null +++ b/hardware/PCB/reference/README.md @@ -0,0 +1,32 @@ +## Adafruit RS-232 Full Pinout Level-Shifter Breakout PCB + +
+Click here to purchase one from the Adafruit shop + +PCB files for the Adafruit RS-232 Full Pinout Level-Shifter Breakout. + +Format is EagleCAD schematic and board layout +* https://www.adafruit.com/product/5988 + +### Description + +If you want to interface with telco, retro, or industrial equipment, you'll probably run into RS-232 interfaces. The Adafruit RS232 Full-Pinout Breakout with 8 Channels of UART to RS-232 Level Shifters is your friend in such cases. It gives you 5 input and 3 output channels of level shifting and takes care of the high/negative voltage generation all in a low-cost breakout board. We use the trusty MAX3243 from TI, a classic chip part of the MAX232 lineage, so you know it will work great for all your RS-232 needs, up to 250Kbps. + +RS-232 is what we had before USB: a 9- or 25-pin D-Sub connector that allowed data plus flow control lines. Many folks may remember these interfaces were used for mice, modems, barcode scanners, teletypes, and more. We still find devices sold with RS-232 ports, although many folks use a USB to RS-232 adapter these days. + +If you want to use a microcontroller or microcomputer to chat with an RS-232, then thankfully, all you need is a serial port / UART (something just about any microcontroller has) and a level shifter. The level shifter is required because while most UARTs are 0-3.3V or 0-5V logic level, RS-232 requires +-6 to +-10V, yep the signal voltage goes negative! That means a specialized shifter is required to generate extra high and low voltages and safely convert the logic levels. + +Sure you could buy a raw MAX232 chip and wire up the necessary capacitors, but this board does it all for you and even comes with a DE-9 connector for plugging in directly into your 'client' device. It can run on 3.3V power and logic, which many older chips can't do. It also can do all 8 data pins, so you can use all of the flow control signals like RTS, CTS, DTR, DSR, DCD and RI. + +We also include two separate lines from the MAX3243: 'Valid' and 'Off'. The Valid line output will have logic level high when the chip detects signal voltages from the device its plugged into. So you can use it as a 'connection made' signal. There's also the Off pin, which when set to logic high by the microcontroller will tri-state all the pins for power reduction. + +This breakout comes fully assembled with a UART side for low-voltage power/logic level, and a DE-9F RS-232 side for high-voltage signals. We also include some header so you can solder to a breadboard in a few minutes. + +### License + +Adafruit invests time and resources providing this open source design, please support Adafruit and open-source hardware by purchasing products from [Adafruit](https://www.adafruit.com)! + +Designed by Limor Fried/Ladyada for Adafruit Industries. + +Creative Commons Attribution/Share-Alike, all text above must be included in any redistribution. +See license.txt for additional details. diff --git a/hardware/PCB/reference/button-omron-b3f-page4.png b/hardware/PCB/reference/button-omron-b3f-page4.png new file mode 100644 index 0000000000000000000000000000000000000000..81dcb4b50925031c861b9b99f7bae2480c10300a GIT binary patch literal 348075 zcmc$`1yGf1+cu1f3M!I~P90<2&RYH> zo03zbIcB;!EOc_aIjCu=FXW~eFlN==Av>ANSh2t2{Cb*-Cf7Fd-P0z;7q5#Z(Nv5s4+l28O{~6fEtpu!_^)Z4^xEZsiTZH%AUAjUr%x|`l;&k+3Gnf$b`(}rRA^{uylV@4NXb@FR`%kQ z?WeM`vhwmoyI*w<4h{msQ&T@a3%OhNmbm%*`(L<>N#0;4Js3>p`eVI4+eGc$xquwU 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HcmV?d00001 diff --git a/hardware/PCB/reference/button-omron-b3f.txt b/hardware/PCB/reference/button-omron-b3f.txt new file mode 100644 index 0000000..ab79060 --- /dev/null +++ b/hardware/PCB/reference/button-omron-b3f.txt @@ -0,0 +1,753 @@ + Tactile Switch B3F +Through-hole-mounting Switches +in a Wide Range of Models: +6 × 6 mm, 12 × 12 mm, Side-operated +Models, Gold-plated Contacts, and +Radial Tape +• Extended mechanical/electrical durability: 10 x 106 + operations for 12 x 12 mm type and 1 x 106 + operations for the 6 x 6 mm type +• Taped radial type, vertical type and high force + types are available. +• Gold plated models available for increased + contact reliability, resistance to corrosive gas and + insulation failure prevention for ion migration in + harsh environments +• B32-series Key Tops mount to models with + projected plungers. +RoHS Compliant + +■ List of Models + +6 × 6 mm Models + Type Contact Plunger Height Operating Plunger Bags + material force (OF) color Without ground Minimum With ground Minimum + terminal packing unit terminal packing unit +Standard: Silver Flat type 4.3 mm 0.98 N {100 gf} lvory B3F-1000 B3F-1100 +B3F-1000 plated 1.47 N {150 gf} Yellow B3F-1002 B3F-1102 +Series + 2.55 N {260 gf} Orange B3F-1005 B3F-1105 + 4.9 N {500 gf} Red B3F-1006 --- + 5.0 mm 0.98 N {100 gf} Black B3F-1020 B3F-1120 + 1.47 N {150 gf} Gray B3F-1022 B3F-1122 + 2.55 N {260 gf} Pink B3F-1025 B3F-1125 + 4.9 N {500 gf} Blue B3F-1026 --- + 5.0 mm 0.98 N {100 gf} Black --- B3F-1110 + (7.5-mm pitch) + 7.0 mm 0.98 N {100 gf} Black B3F-1060 100 pcs --- 100 pcs + 1.47 N {150 gf} Yellow B3F-1062 --- + 9.5 mm 0.98 N {100 gf} Black B3F-1070 --- + 1.47 N {150 gf} Yellow B3F-1072 --- + 2.55 N {260 gf} Orange B3F-1075 --- + 7.3 mm 0.98 N {100 gf} lvory B3F-1050 B3F-1150 + Projected type + 1.47 N {150 gf} Yellow B3F-1052 B3F-1152 + + 2.55 N {260 gf} Orange B3F-1055 B3F-1155 + + 4.9 N {500 gf} Red B3F-1056 --- + + + + + 1 + B3F B3F + + Type Contact Plunger Height Operating Plunger Bags + material force (OF) color Without ground Minimum With ground Minimum + terminal packing unit terminal packing unit +Side- Silver 3.15 mm 0.98 N {100 gf} lvory --- B3F-3100 + Flat type +operated: plated 1.47 N {150 gf} Yellow --- B3F-3102 +B3F-3000 +Series 2.55 N {260 gf} Orange --- B3F-3105 + 3.85 mm 0.98 N {100 gf} Black --- B3F-3120 + 1.47 N {150 gf} Gray --- B3F-3122 + 2.55 N {260 gf} Pink --- B3F-3125 + Projected type 6.15 mm 0.98 N {100 gf} lvory --- B3F-3150 + + 1.47 N {150 gf} Yellow --- B3F-3152 + + 2.55 N {260 gf} Orange --- B3F-3155 + +High- Gold 4.3 mm 1.76 N {180 gf} Yellow B3F-1002-G B3F-1102-G + Flat type +reliability plated +gold-plated: 5.0 mm Gray B3F-1022-G B3F-1122-G +B3F-1000-G 7.0 mm Yellow B3F-1062-G 100 pcs --- 100 pcs +Series (see note) + 9.5 mm Yellow B3F-1072-G --- + (see note) +Side- Projected type 7.3 mm Yellow B3F-1052-G --- +operated +with highly +reliable +gold-plated: +B3F-3000-G +Series + 3.85 mm Gray --- B3F-3122-G + Flat type + (see note) + + + + +Note: Bulk Packaged, 100 Switches per bag. Order in multiples of the package quantity. +12 × 12 mm Models + Type Contact Plunger Height Operating Plunger Bags + material (or LED color) force (OF) color Without ground Minimum With ground Minimum + terminal packing unit terminal packing unit +Standard: Silver Flat type 4.3 mm 1.27 N {130 gf} lvory B3F-4000 B3F-4100 +B3F-4000 plated 2.55 N {260 gf} Yellow B3F-4005 B3F-4105 +Series + Projected type 7.3 mm 1.27 N {130 gf} lvory B3F-4050 B3F-4150 + 2.55 N {260 gf} Yellow B3F-4055 B3F-4155 +Long durability: Silver Flat type 4.3 mm 1.27 N {130 gf} Blue B3F-5000 B3F-5100 + 100 pcs 100 pcs +B3F-5000 Se- plated +ries Projected type 7.3 mm Blue B3F-5050 B3F-5150 +High reliability Gold Flat type 4.3 mm 1.27 N {130 gf} Blue B3F-5001 B3F-5101 +gold-plated: plated +B3F-5001 Projected type 7.3 mm Blue B3F-5051 B3F-5151 +Series +Note: Bulk Packaged, 100 switches per bag. Order in multiples of the package quantity. +6 × 6 mm Radial Models (Taping Specifications) + Type Contact Plunger Height Operating Plunger Taped Radial + material force (OF) color Without ground Minimum With ground Minimum + terminal packing unit terminal packing unit +Taped Silver Flat type 4.3 mm 0.98 N {100 gf} lvory B3F-6000 B3F-6100 +Radial: plated 1.47 N {150 gf} Yellow B3F-6002 B3F-6102 +B3F-6000 +Series 5.0 mm 0.98 N {100 gf} Black B3F-6020 B3F-6120 + 1,000 pcs 1,000 pcs + 1.47 N {150 gf} Gray B3F-6022 B3F-6122 + Projected type 7.3 mm 0.98 N {100 gf} lvory B3F-6050 B3F-6150 + 1.47 N {150 gf} Yellow B3F-6052 B3F-6152 +Note: The switches are tape packaged in units of 1,000 per package. Order in multiples of the package size. Switches are not sold individually. + + + + +2 + B3F B3F + +■ Ratings/Characteristics + +Rating (resistive load) 1 to 50 mA, 3 to 24 VDC (B3F-G: 100 μA to 50 mA, 3 to 24 VDC) +Minimum applicable load (reference value) 10 μA at 1 VDC (resistive load) +Ambient operating temperature -25°C to +70°C at 60%RH max. (with no icing or condensation) +Ambient operating humidity 35% to 85% (at +5 to +35°C) +Contact form SPST-NO +Contact resistance (initial value) 100 mΩ max. +Insulation resistance 100 MΩ min. (at 250 VDC with insulation tester) +Dielectric strength 500 VAC, 50/60 Hz for 1 min +Bounce time 5 ms max. +Vibration resistance Malfunction: 10 to 55 Hz, 1.5 mm double amplitude +Shock resistance Destruction: 1,000 m/s2 {approx. 100G} max. + Malfunction: 100 m/s2 {approx. 10G} max. +Durability B3F-1000, B3F-3000, B3F-6000: + 1,000,000 operations min (OF: 0.98 N {100 gf}) (B3F-1070: 500,000 operations min) + 300,000 operations min (OF: 1.47 N {150 gf}) + 100,000 operations min (OF: 2.55 N {260 gf}) + 50,000 operations min (OF: 4.9 N {500 gf}) + B3F-4000: + 3,000,000 operations min (OF: 1.27 N {130 gf}) + 1,000,000 operations min (OF: 2.55 N {260 gf}) + B3F-5000/5001: + 10,000,000 operations min. + B3F-G: + 300,000 operations min. +Weight 6 × 6 mm models: approx. 0.25 g + 12 × 12 mm models (standard types): approx. 0.85 g + Radial models: approx. 0.25 g +Degree of protection IEC IP00 +Washing Not possible + + +■ Operating Characteristics + +6 × 6 mm Models + B3F-1000, B3F-3000, B3F-6000 B3F-G + Operating force (OF) 0.98 N 1.47 N 2.55 N 4.9 N 1.76 N + B3F-1@@0 B3F-1@@2 B3F-1@@5 B3F-10@6 B3F-1@@2-G +Item B3F-3@@0 B3F-3@@2 B3F-3@@5 B3F-3@@2-G + B3F-6@@0 B3F-6@@2 +Operating force (OF) 0.98±0.29 N 1.47±0.49 N 2.55±0.69 N 4.9±1.47 N 1.76±0.49 N + {100±30 gf} {150±50 gf} {260±70 gf} {500±150 gf} {180±50 gf} +Releasing force (RF) 0.2 N {20 gf} min. 0.49 N {50 gf}min. 0.49 N {50 gf}min. 0.7 N {70 gf} min. 0.49 N {50 gf}min. +Pretravel (PT) 0.25+0.2/–0.1 mm 0.25+0.2/–0.1 mm + + +12 × 12 mm Models + B3F-4000, B3F-5000, B3F-5001 + Operating force (OF) 1.27 N 2.55 N + B3F-4@@0 B3F-4@@5 +Item B3F-5@@0 + B3F-5@@1 +Operating force (OF) 1.27±0.49 N 2.55±0.69 N + {130±50 gf} {260±70 gf} +Releasing force (RF) 0.29 N {30 gf} min. 0.49 N {50 gf} min. +Pretravel (PT) 0.3+0.2/–0.1 mm + + + + + 3 + B3F B3F + +■ Dimensions (Unit: mm) +Note: The numbers used for terminals in the following graphics are indicated in the “Bottom View” diagram below. In this 2 1 + diagram, the Switch is rotated so that the terminals are on the right and left-hand sides, and the OMRON logo ap- 4 3 + pears the right way up. (Except Side-operated and Radial Models) (Bottom View) + +6 × 6 mm Models + +Standard, Flat Plunger Type Standard, Flat Plunger Type +(without Ground Terminal) (with Ground Terminal) +B3F-1000, B3F-1002, B3F-1005, B3F-1006 B3F-1100, B3F-1102, B3F-1105 +B3F-1020 (See note.), B3F-1022 (See note.), B3F-1120 (See note.), B3F-1122 (See note.) +B3F-1025 (See note.), B3F-1026 (See note.) B3F-1125 (See note.) +B3F-1002-G, B3F-1022-G (See note.) B3F-1102-G, B3F-1122-G (See note.) + PCB Processing Dimensions PCB Processing Dimensions + (Reference Only) (Top View) (Reference Only) (Top View) + 6±0.2 (PCB thickness, t=1.6) 6±0.2 (PCB thickness, t=1.6) + + + 6±0.2 4.5±0.2 6±0.2 4.5±0.2 + 4.5±0.1 4.5±0.1 + + 4.1±0.1 + 1.5 3.5 + 6.5±0.1 Four, 1±0.1 dia. dia. Five, 1±0.05 dia. + 3.5 + dia. (See note.) 6.5±0.1 + 4.3±0.2 3.4 + (See note.) Terminal Arrangement/ Terminal Arrangement/Internal + 4.3±0.2 3.4 Internal Connections (Top View) Connections (Top View) + 3.5 + 4 3 0.3 + 3.5 4 3 + 0.3 0.7 + 0.7 0.7 + 6.5±0.5 6.5±0.5 + 0.3 + 7.7±0.5 0.7 0.7 2 1 7.7±0.5 2 1 + Note: The height of B3F-1120, B3F-1122, and 5 + Note: The height of B3F-1020, B3F-1022, B3F-1025, + and B3F-1026 is 5±0.2 mm. B3F-1125 is 5±0.2 mm. + + + +Standard, Flat Plunger Type Standard, Flat Plunger Type +(with Ground Terminal, Pitch: 7.5 mm) (without Ground Terminal) +B3F-1110 B3F-1060, B3F-1062, B3F-1062-G + PCB Processing Dimensions PCB Processing Dimensions + (Reference Only) (Top View) (Reference Only) (Top View) + (PCB thickness, t=1.6) (PCB thickness, t=1.6) + 6±0.2 + 6±0.2 + + 6±0.2 4.5±0.1 + 4.5±0.2 4.5±0.1 + 6±0.2 4.5±0.2 + 4.1±0.1 + + Four, 3.5 + 1.5 1.2±0.05 dia. dia. + 1±0.05 dia. 6.5±0.1 + Four, + 3.5 7.5±0.1 0.5 max. 1±0.05 dia. + dia. + 7±0.2 + Terminal Arrangement/Internal 3.4 + 5±0.2 + 3.4 + Connections (Top View) Terminal Arrangement/ + (1.8) + 3.5 + 4 3 0.3 + Internal Connections + 3.5 (Top View) + 0.3 6.5±0.5 + 7.7±0.5 0.7 0.7 + 4 3 + 0.7 0.7 0.7 2 1 + 7.5±0.5 + 0.3 5 + 9±0.5 + 2 1 + + +Note: Unless otherwise specified, a tolerance of ±0.4 mm applies to all dimensions. No terminal numbers are indicated on the Switches. + + + + +4 + B3F B3F + + +Standard, Flat Plunger Type Standard, Projected Plunger Type +(without Ground Terminal) (without Ground Terminal) +B3F-1070, B3F-1072, B3F-1075, B3F-1072-G B3F-1050, B3F-1052 + B3F-1055, B3F-1056 + PCB Processing Dimensions B3F-1052-G PCB Processing Dimensions + (Reference Only) (Top View) (Reference Only) (Top View) + (PCB thickness, t=1.6) (PCB thickness, t=1.6) + 6±0.2 6±0.2 + + + 6±0.2 4.5±0.2 4.5±0.1 6±0.2 4.5±0.2 4.5±0.2 + + + 3.5 + dia. 6.5±0.1 Four, + 3 6.5±0.1 Four, 2.4 × 2.4±0.1 3.5 dia. 1±0.05 dia. + dia. 1±0.05 .dia + + 0.5 max. Terminal Arrangement/Internal 1.8±0.1 Terminal Arrangement/Internal + 9.5 Connections (Top View) Connections (Top View) + 7.3±0.2 + 3.4 4.3±0.2 3.4 + 4 3 4 3 + (1.8) + 3.5 3.5 + 0.3 0.3 + 6.5±0.5 2 1 6.5±0.5 2 1 + 7.7±0.5 0.7 0.7 0.7 0.7 + 7.7±0.5 + + + +Standard, Projected Plunger Type Side-operated, Flat Plunger Type +(with Ground Terminal) B3F-3100, B3F-3102, B3F-3105 +B3F-1150, B3F-1152, B3F-1155 + + PCB Processing Dimensions PCB Processing Dimensions + (Reference Only) (Top View) (Reference Only) (Top View) + (PCB thickness, t=1.6) 7.3 (PCB thickness, t=1.6) + 6±0.2 + Two, 1.5 ±0.05 dia. + 6.25 + 6±0.2 4.5±0.2 4.5±0.1 + 2.5±0.1 + 4.1±0.1 + 3.5 dia. + 1.5 Five, 1 ±0.05 dia. 4.5±0.1 + 2.4 × 2.4±0.1 3.5 dia. 7±0.1 Two, + 6.5±0.1 1±0.05 dia. + 7.4 + 1.8±0.1 Terminal Arrangement/ Terminal Arrangement/ + 4 + 7.3±0.2 Internal Connections Internal Connections + 4.3±0.2 3.4 (Top View) (Top View) + 3.5 + 4 3 4 + 3.5 0.3 3 + 0.7 0.3 1 + 0.3 4.5±0.5 1 2 + 2 1 2.25 + 0.7 0.7 0.7 7±0.5 2.5±0.5 + 6.5±0.5 5 3.15±0.2 + 0.3 8.7 + 7.7±0.5 + + + +Side-operated, Flat Plunger Type (Height: 3.85 mm) Side-operated, Projected Plunger Type +B3F-3120, B3F-3122, B3F-3125, B3F-3122-G B3F-3150, B3F-3152, B3F-3155 + PCB Processing Dimensions PCB Processing Dimensions + 7.3 7.3 (Reference Only) (Top View) + (Reference Only) (Top View) + (PCB thickness, t=1.6) (PCB thickness, t=1.6) + Two, 1.5 ±0.05 dia. 6.25 Two, 1.5 ±0.05 dia. + 6.25 + + + 2.5±0.1 2.5±0.1 + + 3.5 dia. + 4.5±0.1 4.5±0.1 + 3.5 dia. + 7±0.1 Two, 7±0.1 Two, + 1±0.05 dia. 1±0.05 dia. +7.4 Terminal Arrangement/ 7.4 2.4 × 2.4±0.1 Terminal Arrangement/ + 4 Internal Connections Internal Connections + 4 + (Top View) (Top View) +3.5 + 4 3.5 4 + 3 3 + 0.3 + 0.7 0.3 1 0.3 + 4.5±0.5 1 2 0.7 0.3 1 1 2 + 4.5±0.5 1.8±0.1 + 2.25 + 7±0.5 2.5±0.5 2.25 + 3.85±0.2 7±0.5 2.5±0.5 + 8.7 6.15±0.2 + 8.7 + +Note: Unless otherwise specified, a tolerance of ±0.4 mm applies to all dimensions. No terminal numbers are indicated on the Switches. + + + + + 5 + B3F B3F + +12 × 12 mm Models + Standard, Long-durability, Standard, Long-durability, + and High-reliability Models and High-reliability Models + Flat Plunger Type Flat Plunger Type + (without Ground Terminal) (with Ground Terminal) + B3F-4000, B3F-4005, B3F-4100, B3F-4105, + B3F-5000, B3F-5001 B3F-5100, B3F-5101 + PCB Processing Dimensions PCB Processing Dimensions + (Reference Only) (Top View) (Reference Only) (Top View) + (PCB thickness, t=1.6) (PCB thickness, t=1.6) + Two, 1.8±0.05 dia. + Two, 1.8±0.05 dia. (for positioning boss) + 12±0.2 (for positioning boss) 12±0.2 + + + 5±0.1 9±0.1 + 5±0.1 9±0.1 + 12±0.2 5±0.2 12±0.2 5±0.2 + 6.9±0.1 + + Five, + Four, 1.2±0.05 dia. + 12.5±0.1 1.2±0.05 dia. + 1.6 12.5±0.1 + + + 7.1 dia. + Terminal Arrangement/ Terminal Arrangement/ + 7.1 dia. + Internal Connections Internal Connections + 4.3±0.2 + (Top View) (Top View) + 3.5 4.3±0.2 3.5 + 3.5 4 3 4 3 + 3.5 + 1.6 dia. 1.6 dia. + 0.3 1 1 0.9 0.3 1 1 + 12.5±0.5 9±0.1 2 1 12.5±0.5 6.9 2 1 + 13.8±0.5 13.8±0.5 9±0.1 5 + + + + +Standard, Long-durability, Standard, Long-durability, +and High-reliability Models and High-reliability Models +Projected Plunger Type Projected Plunger Type +(without Ground Terminal) (with Ground Terminal) +B3F-4050, B3F-4055, B3F-4150, B3F-4155, +B3F-5050, B3F-5051 PCB Processing Dimensions B3F-5150, B3F-5151 PCB Processing Dimensions + (Reference Only) (Top View) (Reference Only) (Top View) + (PCB thickness, t=1.6) (PCB thickness, t=1.6) + 12±0.2 Two, 1.8±0.05 dia. + Two, 1.8±0.05 dia. + (for positioning boss) (for positioning boss) + 12±0.2 + + 12±0.2 5±0.2 + 5±0.1 9±0.1 + 5±0.1 9±0.1 + 12±0.2 5±0.2 + 6.9±0.1 + + 1.6 Five, + Four, 1.2±0.05 dia. + 12.5±0.1 1.2±0.05 dia. + @3.8±0.1 12.5±0.1 + @3.8±0.1 + 7.1 dia. 7.1 dia. + + Terminal Arrangement/ 1.8±0.2 Terminal Arrangement/ + 1.8±0.2 + Internal Connections 7.3±0.2 Internal Connections +7.3±0.2 + 4.3±0.2 3.5 (Top View) 4.3±0.2 3.5 (Top View) + 3.5 4 3 3.5 4 3 + + 1.6 dia. 1.6 dia. + 0.3 1 1 0.9 0.3 1 1 + 12.5±0.5 9±0.1 2 1 12.5±0.5 6.9 2 1 + 13.8±0.5 13.8±0.5 9±0.1 + 5 + + + + +Note: Unless otherwise specified, a tolerance of ±0.4 mm applies to all dimensions. + + + + +6 + B3F B3F + +Note: The numbers used for terminals in the following graphics are indicated in the “Bottom View” diagram below. In this 1 + diagram, the Switch is rotated so that the terminals are on the right and left-hand sides, and the OMRON logo appears + the right way up. + 2 +6 mm × 6 mm Radial Types (Taping Specifications): Sold in Units of 1,000 Switches + (Bottom View) + + +Flat Plunger Type 6±0.3 Surface B +(without Ground Terminal) +B3F-6000, B3F-6002 6±0.3 + 12.7±1 + 6.35±1 + 2 max. + 3.5 dia. Surface A + + 0.5 max. + Support + 0.9 tape 9 + (1) 4.3 0.5 max. +1 + 3.4 180 + + 6 + 0.2 max. 9±0.5 + 0.5 + +1 + 5-0.2 + +0.8 0.3 18-0.5 + + 4 dia. ±0.2 + Terminal Arrangement + PCB Processing Dimensions /Internal Connections + 12.7±0.3 Carrier tape + (Reference Only) (Top View) (Top View) + Note: The tape is random + (PCB thickness, t=1.6) + between surface A + and surface B. + +0.1 2 1 + Two, 1 0 dia. 5±0.1 + + + + +Flat Plunger Type 6±0.3 12.7±1 + 6.35±1 +(with Ground Terminal) 2 max. +B3F-6100, B3F-6102 6±0.3 2 + + + 3.5 dia. + Support 11 + 0.5 max. tape 0.5 max. + 20±0.5 + 0.9 + (1) 4.3 3.4 + 6 + 9±0.5 + 3.1 + +1 + 0.2 dia. 18-0.5 + 0.5 5±0.2 0.3 + +0.8 4±0.2 dia. + 5-0.2 0.6 + + + 12.7±0.3 Carrier tape + PCB Processing Dimensions Terminal Arrangement + (Reference Only) (Top View) /Internal Connections + (PCB thickness, t=1.6) (Top View) + + + + +0.1 2 1 + Three, 1 0 dia. 5±0.1 3 + 5±0.1 + + + + Flat Plunger Type 6±0.3 Surface B + (without Ground Terminal) 12.7±1 + B3F-6020, B3F-6022 6.35±1 + 2 max. + 6±0.3 + + + 3.5 dia. Surface A + Support 9 + 0.5 max. tape 0.5 max. +1 + 180 + 0.9 + (1) 5 + 3.4 6 + 9±0.5 + +1 + 0.2 max. 18-0.5 + 0.5 + +0.8 + 5-0.2 0.3 4±0.2 dia. + + Terminal Arrangement Carrier tape + Note: The tape is random PCB Processing Dimensions /Internal Connections + 12.7±0.3 + + between surface A (Reference Only) (Top View) (Top View) + and surface B. (PCB thickness, t=1.6) + + + +0.1 2 1 + Two, 1 0 dia. 5±0.1 + + + +Note: Unless otherwise specified, a tolerance of ±0.4 mm applies to all dimensions. No terminal numbers are indicated on the Switches. + + + + 7 + B3F B3F + + +Flat Plunger Type 6±0.3 +(with Ground Terminal) +B3F-6120, B3F-6122 6±0.3 2 + 12.7±1 + 6.35±1 + 2 max. + + 3.5 dia. + 0.5 max. + + 0.9 Support 11 + (1) 5 + 3.4 tape 0.5 max. + 20±0.5 + 3.1 + 0.2 max. 6 + 9±0.5 + 0.5 5±0.2 0.3 + +1 + +0.8 + 5-0.2 0.6 18-0.5 + + 4±0.2 dia. + PCB Processing Dimensions Terminal Arrangement + (Reference Only) (Top View) /Internal Connections Carrier tape + 12.7±0.3 + (PCB thickness, t=1.6) (Top View) + + + +0.1 2 1 + Three, 1 0 dia. 5±0.1 3 + 5±0.1 + + + + +Projected Plunger Type 6±0.3 Surface B +(without Ground Terminal) +B3F-6050, B3F-6052 + 6±0.3 + + 12.7±1 + 3.5 dia. Surface A 6.35±1 + 2.4 2 max. + + + 0.5 max. + 7.3 0.9 + (1) 3.4 + Support 9 + tape 0.5 dia. +1 + 18 0 + 0.2 max. + 0.5 + +0.8 0.3 6 + 5-0.2 9±0.5 + +1 + 18-0.5 + PCB Processing Dimensions Terminal Arrang ement + (Reference Only) (Top View) /Internal Connections 4±0.2 dia. + (PCB thickness, t=1.6) (Top View) + 12.7±0.3 Carrier tape + +0.1 + Two, 1 0 dia. 5±0.1 2 1 + + + Note: The tape is random between surface A + and surface B. + + + Projected Plunger Type 6±0.3 + (with Ground Terminal) + B3F-6150, B3F-6152 + 6±0.3 2 12.7±1 + 6.35±1 + 2 max. + + 3.5 dia. 2.4 + + + 0.5 max. + 7.3 0.9 + (1) 3.4 Support 11 + tape 0.5 max. + 20±0.5 + 3.1 + 0.2 max. + 6 + 9±0.5 + 0.5 5±0.2 0.3 + +0.8 +1 + 5 -0.2 0.6 18-0.5 + + + Terminal Arrangement 4±0.2 dia. + PCB Processing Dimensions + (Reference Only) (Top View) /Internal Connections + (PCB thickness, t=1.6) (Top View) 12.7±0.3 Carrier tape + + + + +0.1 + Three, 1 0 dia. 5±0.1 2 1 + 3 + 5±0.1 + + + +Note: Unless otherwise specified, a tolerance of ±0.4 mm applies to all dimensions. No terminal numbers are indicated on the Switches. + + + +8 + B3F B3F + +■ Key Tops +B32-series Key Tops are available for projected plungers. Refer to the Datasheet of B32 for details. + +■ Precautions +Be sure to read the safety precautions common to all Tactile Switches for correct use. + + + + +• Application examples provided in this document are for reference only. In actual applications, confirm equipment functions and safety before using the product. +• Consult your OMRON representative before using the product under conditions which are not described in the manual or applying the product to nuclear control systems, railroad + systems, aviation systems, vehicles, combustion systems, medical equipment, amusement machines, safety equipment, and other systems or equipment that may have a serious + influence on lives and property if used improperly. Make sure that the ratings and performance characteristics of the product provide a margin of safety for the system or + equipment, and be sure to provide the system or equipment with double safety mechanisms. + + + Note: Do not use this document to operate the Unit. + +OMRON Corporation +Electronic and Mechanical Components Company Contact: www.omron.com/ecb Cat. No. A070-E1-08 + 1014(0207)(O) + + + + 9 + \ No newline at end of file diff --git a/hardware/PCB/reference/license.txt b/hardware/PCB/reference/license.txt new file mode 100644 index 0000000..1d1e1d6 --- /dev/null +++ b/hardware/PCB/reference/license.txt @@ -0,0 +1,359 @@ +Creative Commons Legal Code + +Attribution-ShareAlike 3.0 Unported + + CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE + LEGAL SERVICES. DISTRIBUTION OF THIS LICENSE DOES NOT CREATE AN + ATTORNEY-CLIENT RELATIONSHIP. CREATIVE COMMONS PROVIDES THIS + INFORMATION ON AN "AS-IS" BASIS. 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For the avoidance of doubt, + this trademark restriction does not form part of the License. + + Creative Commons may be contacted at https://creativecommons.org/. \ No newline at end of file diff --git a/hardware/PCB/route_pcb_draft.py b/hardware/PCB/route_pcb_draft.py new file mode 100644 index 0000000..d7a922b --- /dev/null +++ b/hardware/PCB/route_pcb_draft.py @@ -0,0 +1,365 @@ +#!/usr/bin/python3 +"""Bounded, board-specific two-layer draft router. Requires pcbnew and numpy. + +Dry-run by default. --route --overwrite explicitly permits saving routing; +existing copper additionally requires --replace-routes. Never edits the project, +schematic, footprint libraries or generator. Review actual KiCad DRC afterwards. +This is not a production autorouter or a fabrication qualification. +""" +import argparse +from collections import defaultdict +import hashlib +import heapq +import json +import math +from pathlib import Path +import time + +import numpy as np +import pcbnew as p + +ROOT = Path(__file__).resolve().parent +PCB = ROOT / 'serial-carrier.kicad_pcb' +STEP = 0.05 +NX, NY = int(82 / STEP) + 1, int(80 / STEP) + 1 +N = NX * NY +CLEARANCE = 0.25 +MARGIN = 0.02 +LAYERS = (p.F_Cu, p.B_Cu) +X = 100 + np.arange(NX)[None, :] * STEP +Y = 100 + np.arange(NY)[:, None] * STEP + + +def mm(v): + return p.FromMM(v) + + +def point(xy): + return p.VECTOR2I(mm(xy[0]), mm(xy[1])) + + +def pos(item): + v = item.GetPosition() + return (p.ToMM(v.x), p.ToMM(v.y)) + + +def identity(board): + """Immutable geometry/linkage snapshot, independent of serialization order.""" + footprints = [] + for f in board.GetFootprints(): + pads = sorted((a.m_Uuid.AsString(), a.GetNumber(), a.GetNetname(), + pos(a), (a.GetSize().x, a.GetSize().y), + (a.GetDrillSize().x, a.GetDrillSize().y), + a.GetShape(), a.GetAttribute(), a.GetLayerSet().FmtHex(), + a.GetOrientationDegrees(), a.GetPinFunction(), a.GetPinType()) + for a in f.Pads()) + footprints.append((f.m_Uuid.AsString(), f.GetReference(), f.GetValue(), + f.GetFPIDAsString(), f.GetPath().AsString(), pos(f), + f.GetOrientationDegrees(), f.GetLayer(), pads)) + edges = sorted((a.m_Uuid.AsString(), a.GetShape(), a.GetStart().x, + a.GetStart().y, a.GetEnd().x, a.GetEnd().y, a.GetWidth()) + for a in board.GetDrawings() if a.GetLayer() == p.Edge_Cuts) + zones = sorted((z.m_Uuid.AsString(), z.GetLayerSet().FmtHex(), + z.GetIsRuleArea(), z.GetDoNotAllowTracks(), + z.GetDoNotAllowVias(), z.GetDoNotAllowZoneFills(), + tuple((z.Outline().COutline(0).CPoint(i).x, + z.Outline().COutline(0).CPoint(i).y) + for i in range(z.Outline().COutline(0).PointCount()))) + for z in board.Zones()) + nets = sorted((n.GetNetCode(), n.GetNetname()) for n in board.GetNetsByNetcode().values()) + return (board.GetCopperLayerCount(), sorted(footprints), edges, zones, nets) + + +def window(x0, y0, x1, y1): + ix0 = max(0, int(math.floor((x0 - 100) / STEP))) + iy0 = max(0, int(math.floor((y0 - 100) / STEP))) + ix1 = min(NX, int(math.ceil((x1 - 100) / STEP)) + 1) + iy1 = min(NY, int(math.ceil((y1 - 100) / STEP)) + 1) + return slice(iy0, iy1), slice(ix0, ix1) + + +def capsule(mask, a, b, radius): + sy, sx = window(min(a[0], b[0]) - radius, min(a[1], b[1]) - radius, + max(a[0], b[0]) + radius, max(a[1], b[1]) + radius) + xx, yy = X[:, sx], Y[sy, :] + dx, dy = b[0] - a[0], b[1] - a[1] + length2 = dx * dx + dy * dy + t = np.clip(((xx - a[0]) * dx + (yy - a[1]) * dy) / length2, 0, 1) if length2 else 0 + mask[sy, sx] |= (xx - a[0] - t * dx)**2 + (yy - a[1] - t * dy)**2 <= radius**2 + + +def pad_obstacle(mask, pad, extra, hole_only=False): + xy = pos(pad) + size = pad.GetDrillSize() if hole_only else pad.GetSize() + rx, ry = p.ToMM(size.x) / 2, p.ToMM(size.y) / 2 + if not rx or not ry: + return + if abs(rx - ry) < 1e-6 and (hole_only or pad.GetShape() == p.PAD_SHAPE_CIRCLE): + capsule(mask, xy, xy, rx + extra) + else: + # Bounding rectangle deliberately overestimates non-circular pad shapes. + box = pad.GetBoundingBox() + x0, y0 = p.ToMM(box.GetX()) - extra, p.ToMM(box.GetY()) - extra + x1, y1 = p.ToMM(box.GetRight()) + extra, p.ToMM(box.GetBottom()) + extra + sy, sx = window(x0, y0, x1, y1) + mask[sy, sx] |= (X[:, sx] >= x0) & (X[:, sx] <= x1) & (Y[sy, :] >= y0) & (Y[sy, :] <= y1) + + +def boundary(radius): + edge = 0.5 + radius + MARGIN + mask = np.broadcast_to((X < 100 + edge) | (X > 182 - edge) | + (Y < 100 + edge) | (Y > 180 - edge), (NY, NX)).copy() + mask |= (X < 136 + edge) & (Y > 161 - edge) + # Expand the RF reservation by copper radius plus numerical safety margin. + r = radius + MARGIN + mask |= (X >= 110 - r) & (X <= 131 + r) & (Y <= 113 + r) + return mask + + +def masks(board, pads, net, width): + blocked = np.stack([boundary(width / 2)] * 2) + via = boundary(0.35) + for pad in pads: + if pad.GetNetCode() != net or not pad.GetNumber(): + for z, layer in enumerate(LAYERS): + if pad.IsOnLayer(layer): + pad_obstacle(blocked[z], pad, CLEARANCE + width / 2 + MARGIN) + pad_obstacle(via, pad, CLEARANCE + 0.35 + MARGIN) + # Even same-net holes must not receive a drilled via. + pad_obstacle(via, pad, CLEARANCE + 0.35 + MARGIN, hole_only=True) + for track in board.GetTracks(): + if track.GetNetCode() == net: + if isinstance(track, p.PCB_VIA): + capsule(via, pos(track), pos(track), 0.7 + CLEARANCE + MARGIN) + continue + a = (p.ToMM(track.GetStart().x), p.ToMM(track.GetStart().y)) + b = (p.ToMM(track.GetEnd().x), p.ToMM(track.GetEnd().y)) + radius = p.ToMM(track.GetWidth(p.F_Cu) if isinstance(track, p.PCB_VIA) else track.GetWidth()) / 2 + for z, layer in enumerate(LAYERS): + if isinstance(track, p.PCB_VIA) or track.GetLayer() == layer: + capsule(blocked[z], a, b, radius + CLEARANCE + width / 2 + MARGIN) + capsule(via, a, b, radius + CLEARANCE + 0.35 + MARGIN) + return blocked.reshape(-1), via.reshape(-1) + + +def node(xy, layer=0): + x, y = (int(round((v - 100) / STEP)) for v in xy) + return layer * N + y * NX + x + + +def decode(i): + z, q = divmod(i, N) + y, x = divmod(q, NX) + return (100 + x * STEP, 100 + y * STEP), z + + +def astar(blocked, via, start, target, deadline, max_expansions): + tx = int(round((target[0] - 100) / STEP)) + ty = int(round((target[1] - 100) / STEP)) + targetq = ty * NX + tx + + def h(q): + y, x = divmod(q, NX) + dx, dy = abs(x - tx), abs(y - ty) + return 10 * max(dx, dy) + 4 * min(dx, dy) + + dist = np.full(2 * N, 2147483647, dtype=np.int32) + parent = np.full(2 * N, -1, dtype=np.int32) + heap = [] + for z in (0, 1): + i = node(start, z) + if not blocked[i]: + dist[i] = 0 + heapq.heappush(heap, (h(i % N), 0, i)) + expanded = 0 + moves = ((1, 0, 10), (-1, 0, 10), (0, 1, 10), (0, -1, 10), + (1, 1, 14), (1, -1, 14), (-1, 1, 14), (-1, -1, 14)) + while heap: + _, cost, i = heapq.heappop(heap) + if cost != dist[i]: + continue + z, q = divmod(i, N) + if q == targetq: + path = [i] + while parent[path[-1]] >= 0: + path.append(int(parent[path[-1]])) + return path[::-1], expanded + expanded += 1 + if expanded >= max_expansions or (expanded % 1024 == 0 and time.monotonic() >= deadline): + return None, expanded + y, x = divmod(q, NX) + for dx, dy, stepcost in moves: + if not (0 <= x + dx < NX and 0 <= y + dy < NY): + continue + j = i + dy * NX + dx + if blocked[j] or (dx and dy and (blocked[i + dx] or blocked[i + dy * NX])): + continue + # Mild layer preference prevents needless coincident layer choices. + penalty = int((z == 0 and dx == 0) or (z == 1 and dy == 0)) + nc = cost + stepcost + penalty + if nc < dist[j]: + dist[j], parent[j] = nc, i + heapq.heappush(heap, (nc + h(j % N), nc, j)) + j = (1 - z) * N + q + if not via[q] and not blocked[j]: + nc = cost + int(18 / STEP) # 1.8 mm equivalent cost for a layer change. + if nc < dist[j]: + dist[j], parent[j] = nc, i + heapq.heappush(heap, (nc + h(q), nc, j)) + return None, expanded + + +def add_path(board, path, start, target, net, width): + points = [decode(i) for i in path] + points = [(start, points[0][1])] + points + [(target, points[-1][1])] + # Only merge exactly collinear grid runs; never shortcut obstacle checks. + simple = [] + for item in points: + if simple and item == simple[-1]: + continue + while len(simple) >= 2 and item[1] == simple[-1][1] == simple[-2][1]: + a, b, c = simple[-2][0], simple[-1][0], item[0] + cross = (b[0]-a[0])*(c[1]-b[1]) - (b[1]-a[1])*(c[0]-b[0]) + dot = (b[0]-a[0])*(c[0]-b[0]) + (b[1]-a[1])*(c[1]-b[1]) + if abs(cross) > 1e-8 or dot < 0: + break + simple.pop() + simple.append(item) + for (a, z), (b, zz) in zip(simple, simple[1:]): + if z != zz: + assert a == b + item = p.PCB_VIA(board) + item.SetPosition(point(a)) + item.SetWidth(mm(0.7)) + item.SetDrill(mm(0.3)) + item.SetViaType(p.VIATYPE_THROUGH) + item.SetLayerPair(p.F_Cu, p.B_Cu) + else: + if a == b: + continue + item = p.PCB_TRACK(board) + item.SetStart(point(a)) + item.SetEnd(point(b)) + item.SetWidth(mm(width)) + item.SetLayer(LAYERS[z]) + item.SetNetCode(net) + board.Add(item) + + +def pairs_for_net(pads): + # Minimum spanning tree includes duplicate switch contacts explicitly. + connected = {0} + todo = set(range(1, len(pads))) + pairs = [] + while todo: + length, a, b = min((math.dist(pos(pads[a]), pos(pads[b])), a, b) + for a in connected for b in todo) + pairs.append((length, pads[a], pads[b])) + connected.add(b) + todo.remove(b) + return pairs + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument('--route', action='store_true') + parser.add_argument('--overwrite', action='store_true') + parser.add_argument('--replace-routes', action='store_true') + parser.add_argument('--seconds', type=float, default=240) + parser.add_argument('--max-expansions', type=int, default=1200000) + args = parser.parse_args() + if args.route and not args.overwrite: + parser.error('--route requires --overwrite; back up manual routing first') + if not 0 < args.seconds <= 900 or not 0 < args.max_expansions <= 1500000: + parser.error('bounds: seconds (0,900], max-expansions (0,1500000]') + if ROOT.joinpath('~serial-carrier.kicad_pcb.lck').exists(): + parser.error('PCB editor lock exists; close the PCB before routing') + original_bytes = PCB.read_bytes() + board = p.LoadBoard(str(PCB)) + before = identity(board) + if board.GetCopperLayerCount() != 2 or len(board.GetFootprints()) != 13: + parser.error('unexpected board structure; review router assumptions') + if len(board.Zones()) != 1 or not board.Zones()[0].GetIsRuleArea(): + parser.error('unexpected zones; router supports only the original RF rule area') + outline = [(100, 100), (182, 100), (182, 180), (136, 180), (136, 161), (100, 161)] + expected_edges = {frozenset((a, b)) for a, b in zip(outline, outline[1:] + outline[:1])} + actual_edges = {frozenset(((p.ToMM(e.GetStart().x), p.ToMM(e.GetStart().y)), + (p.ToMM(e.GetEnd().x), p.ToMM(e.GetEnd().y)))) + for e in board.GetDrawings() if e.GetLayer() == p.Edge_Cuts} + if actual_edges != expected_edges: + parser.error('outline differs from the board-specific routing envelope') + reserve = board.Zones()[0] + contour = reserve.Outline().COutline(0) + rf_points = {(p.ToMM(contour.CPoint(i).x), p.ToMM(contour.CPoint(i).y)) + for i in range(contour.PointCount())} + if (rf_points != {(110, 100), (131, 100), (131, 113), (110, 113)} or + not all(reserve.IsOnLayer(layer) for layer in LAYERS) or + not all((reserve.GetDoNotAllowTracks(), reserve.GetDoNotAllowVias(), + reserve.GetDoNotAllowZoneFills()))): + parser.error('RF rule area differs from the board-specific reservation') + if board.GetTracks() and not args.replace_routes: + parser.error('existing routing protected; --replace-routes required even for preview') + for track in list(board.GetTracks()): + board.Delete(track) + pads = [a for f in board.GetFootprints() for a in f.Pads()] + if any(a.GetOrientationDegrees() % 90 or not all(a.IsOnLayer(l) for l in LAYERS) for a in pads): + parser.error('router requires axis-aligned through-hole pads') + nets = defaultdict(list) + for pad in pads: + if pad.GetNumber() and pad.GetNetCode(): + nets[pad.GetNetCode()].append(pad) + work = [] + for net, netpads in nets.items(): + if len(netpads) > 1: + name = netpads[0].GetNetname() + for length, a, b in pairs_for_net(netpads): + # Short local links first, then the long signal fanout; ground last. + priority = (name == '/GND', length) + work.append((priority, net, name, a, b)) + work.sort(key=lambda w: (w[0], w[2])) + start_time = time.monotonic() + deadline = start_time + args.seconds + results = [] + for _, net, name, a, b in work: + width = 0.5 if name in ('/+3V3', '/GND') else 0.25 + path, expanded = None, 0 + if time.monotonic() < deadline: + blocked, via = masks(board, pads, net, width) + path, expanded = astar(blocked, via, pos(a), pos(b), deadline, args.max_expansions) + fallback = False + if path is None and width == 0.5 and time.monotonic() < deadline: + width, fallback = 0.25, True + blocked, via = masks(board, pads, net, width) + path, more = astar(blocked, via, pos(a), pos(b), deadline, args.max_expansions) + expanded += more + label = lambda pad: pad.GetParentFootprint().GetReference() + '.' + pad.GetNumber() + result = dict(net=name, start=label(a), end=label(b), start_mm=pos(a), end_mm=pos(b), + routed=path is not None, width_mm=width, power_fallback=fallback, expansions=expanded) + results.append(result) + if path is not None: + add_path(board, path, pos(a), pos(b), net, width) + print(json.dumps(result), flush=True) + assert identity(board) == before, 'immutable board data changed' + report = dict(draft_only=True, saved=args.route, grid_mm=STEP, clearance_mm=CLEARANCE, + safety_margin_mm=MARGIN, via_diameter_mm=0.7, via_drill_mm=0.3, + elapsed_seconds=time.monotonic()-start_time, connections=results, + routed_tree_edges=sum(r['routed'] for r in results), total_tree_edges=len(results), + tracks=sum(not isinstance(t, p.PCB_VIA) for t in board.GetTracks()), + vias=sum(isinstance(t, p.PCB_VIA) for t in board.GetTracks()), + immutable_identity_sha256=hashlib.sha256(repr(before).encode()).hexdigest(), + input_sha256=hashlib.sha256(original_bytes).hexdigest(), + validation='KiCad DRC must be run separately; tree-edge counts are not DRC connectivity') + if args.route: + if PCB.read_bytes() != original_bytes or ROOT.joinpath('~serial-carrier.kicad_pcb.lck').exists(): + raise RuntimeError('PCB changed or editor opened during routing; refusing overwrite') + # Check a serialized candidate before replacing the user's board. + candidate = ROOT / 'validation/pcb-routing-candidate.kicad_pcb' + p.SaveBoard(str(candidate), board) + assert identity(p.LoadBoard(str(candidate))) == before, 'saved identity mismatch' + candidate.replace(PCB) + ROOT.joinpath('validation/pcb-routing-run.json').write_text(json.dumps(report, indent=2)+'\n') + print(json.dumps({k: v for k, v in report.items() if k != 'connections'}, indent=2)) + + +if __name__ == '__main__': + main() diff --git a/hardware/PCB/rs232-footprint-notes.md b/hardware/PCB/rs232-footprint-notes.md new file mode 100644 index 0000000..a9ba533 --- /dev/null +++ b/hardware/PCB/rs232-footprint-notes.md @@ -0,0 +1,117 @@ +# MAX3243 carrier — PROVISIONAL female CAD reference / VERIFY MALE + +Footprint: `Carrier:MAX3243_Reference_Provisional` in +`Carrier.pretty/MAX3243_Reference_Provisional.kicad_mod`. +Intended only for a <=100 × 100 mm, two-copper-layer carrier PCB draft. +No schematic assignment or edits are made. This footprint does not establish +whole-board fit, connector access, DRC compliance, or fabrication readiness. + +## Evidence and scope + +The user reports that the male **6253** module has the same dimensions. This is +not confirmation of its pad map. Geometry below is taken from published **female +5988** Eagle CAD, not verified male-specific CAD. Confirm the purchased module's +identity, orientation, header numbering, outline and mounting geometry before +release. Never infer header order from DE-9 gender or mating-face numbering. + +Source: [Adafruit PCB repository](https://github.com/adafruit/Adafruit-RS-232-Level-Shifter-Breakout-PCB), +commit `63c6200bb3ef17d491089cfa6441b1810d79bb20`. +Local original: `reference/Adafruit RS-232 Full Pinout Level-Shifter Breakout.brd`; +SHA-256 `6a7b35ef909f5a2d243c326c34db3957aaa01275bf2aac8e0c749ff18162e870` +was rechecked against the file. See `adafruit-research.md` for provenance and +female/male distinctions. + +CAD-derived geometry adapted from the design by **Limor Fried/Ladyada for Adafruit +Industries**, under **CC BY-SA 3.0 Unported**: +https://creativecommons.org/licenses/by-sa/3.0/ . The CAD-derived footprint and +these CAD-derived notes use that license. Preserve the full upstream notices in +`reference/README.md` and `reference/license.txt` when redistributing this adaptation. +Changes: coordinate transformation, carrier pad convention, NPTH carrier holes, +and provisional annotations; no module circuitry or connector package copied. + +## View, origin and exact nominal geometry + +Front/component top view, module facing up, DE-9 toward the top (**negative Y**). +Origin is header JP2 pin 1, not a PCB corner. X increases rightward; Y downward. +Transform Eagle board coordinates in mm with: + +`x = X - 1.905; y = 2.667 - Y`. + +- Pads 1…12: `(2.54 × (N - 1), 0)`, first-to-last span 27.94 mm. +- Full bare-module outline is on `F.Fab`, **not carrier `Edge.Cuts`**. + Bounds: X = -1.905…29.845, Y = -26.670…2.667 (31.750 × 29.337 mm). + Top corners are square. Bottom corners retain the source 2.540 mm radius arcs. +- Left arc: (-1.905, 0.127) to (0.635, 2.667), centre (0.635, 0.127). + Right arc: (27.305, 2.667) to (29.845, 0.127), centre (27.305, 0.127). + Midpoints use radius/sqrt(2), rounded to nine decimal places in the file; + the arcs are not chamfers or a bounding-box approximation. +- Two unnumbered **3.00 mm NPTH carrier holes**: (1.905, -8.763) and + (26.035, -8.763), spacing 24.130 mm. These transfer module-hole centres and + drill diameter only. The source module holes are actually plated, 3.60 mm + copper / 3.00 mm drill, unconnected in the source signal map. Carrier NPTH + deliberately does not copy that plating or assign electrical connections. + No screw, washer, standoff or tool-access clearance is implied. + +## Provisional carrier pads and female reference map + +Same convention documented in `footprint-notes.md` for the other carrier modules: +**1.70 × 1.70 mm PTH pads / 1.00 mm drills**, rectangular pad 1, circular pads +2…12, `*.Cu` and `*.Mask`, unused copper layers retained. That convention derives +from the installed KiCad `PinHeader_1x04_P2.54mm_Vertical`; it is not a selected +header/socket qualification. The source module itself uses 1.9304 mm round pads. +Confirm actual pins/sockets, finished-hole tolerances, annular rings and assembly +height before fabrication. Square pad 1 is a carrier marker, not source evidence. + +| Pad | X (mm), Y=0 | Female label | Female CAD net | +|---:|---:|---|---| +| 1 | 0.00 | Vin | VCC | +| 2 | 2.54 | GND | GND | +| 3 | 5.08 | DCD | DCD | +| 4 | 7.62 | RX | RXD | +| 5 | 10.16 | TX | TXD | +| 6 | 12.70 | DTR | DTR | +| 7 | 15.24 | DSR | DSR | +| 8 | 17.78 | RTS | RTS | +| 9 | 20.32 | CTS | CTS | +| 10 | 22.86 | RI | RI | +| 11 | 25.40 | VLD | !INVALID | +| 12 | 27.94 | OFF | !FORCEOFF | + +**This is the female reference map, NOT a confirmed male map.** Footprint pads +have numbers only, no assigned nets. OFF is active low; VLD indicates valid input +when high. This project's logic interface requires 3.3 V Vin. + +## Intentionally omitted / release gates + +**No verified DE-9 mechanical envelope is available, so none is drawn.** No +male overhang, shell, mating plug, cable bend, enclosure cutout, height, underside +keepout, mounting-hardware clearance, 3D model or courtyard is invented. Female +library silkscreen and product bounding dimensions are not male clearance data. +The F.Fab outline describes only the bare module PCB, not the assembled envelope. +There is **no fake courtyard**; courtyard checks cannot establish assembly fit. +Short silkscreen labels identify PROVISIONAL / FEMALE CAD REF / VERIFY MALE. + +Before layout release: verify male pad map and orientation against the actual +module or authoritative male CAD; perform a 1:1 fit check; select headers and +mounting hardware; verify assembled and mating envelopes; then establish real +clearances/courtyard and check the complete <=100 × 100 mm two-layer layout. + +## Validation performed + +KiCad **10.0.6** `pcbnew.FootprintLoad` successfully loaded the footprint using +system Python (`/usr/bin/python3 -B`) in a read-only inline check. Assertions passed +for all 12 numbered pad positions against source JP2 package/element coordinates, +female signal-contactref order, pad sizes/drills/shapes and copper/mask presence, +no assigned header nets, both NPTH centres/sizes/drills, and all six transformed +source outline segments including both 90-degree, 2.540 mm radius arcs and centres. +Also checked absence of courtyard, Edge.Cuts, zones and 3D models. + +The first check assumed arc endpoint order was preserved; KiCad normalizes arc +orientation. The corrected check matches endpoint pairs independent of order and +verifies radius, angle and centre; it passed without changing geometry. The +binding emitted the same three startup `PROPERTY_ENUM` assertions documented for +other module validation; these did not prevent loading or successful checks. +No hardware fit test, male electrical verification, board DRC or firmware build +was performed. Existing `validate_footprints.py` was not changed and does not +cover this new footprint. Only this notes file and the new footprint were written; +schematic, project and lock files were left untouched. diff --git a/hardware/PCB/serial-carrier.kicad_pcb b/hardware/PCB/serial-carrier.kicad_pcb new file mode 100644 index 0000000..55b073e --- /dev/null +++ b/hardware/PCB/serial-carrier.kicad_pcb @@ -0,0 +1,7954 @@ +(kicad_pcb + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (general + (thickness 1.6) + (legacy_teardrops no) + ) + (paper "A4") + (title_block + (title "Serial Swiss Army Knife - 82x80 mm carrier draft") + (rev "A0 DRAFT") + (comment 1 "NOT FOR FABRICATION - male module / USB / antenna geometry unverified") + ) + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting + (front yes) + (back yes) + ) + (covering + (front no) + (back no) + ) + (plugging + (front no) + (back no) + ) + (capping no) + (filling no) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12) + (dashed_line_gap_ratio 3) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (footprint "Button_Switch_THT:SW_TH_Tactile_Omron_B3F-100x" + (layer "F.Cu") + (uuid "1545d15f-20f4-4a6a-a25e-c8bbaa98b280") + (at 155 168) + (descr "Tactile switch, 6x6 mm, H4.3 mm, 6.5 mm pitch, https://omronfs.omron.com/en_US/ecb/products/pdf/en-b3f.pdf") + (tags "Omron B3F-10xx SPST 1P1T") + (property "Reference" "SW2" + (at 3.25 -2 0) + (layer "F.SilkS") + (uuid "0464527f-fc60-4cc8-8e54-de5d4f9d1e82") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" 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"F.SilkS") + (hide yes) + (uuid "769482c4-e8d8-4700-b7f3-899603f4f2b0") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Procurement" "Live stock not verified" + (at 0 0 0) + (layer "F.SilkS") + (hide yes) + (uuid "5c19bcf2-9483-4cd5-bb8d-b4e61d5fceed") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (path "/c86e0d56-4290-5f2b-b790-14926c8cdeea/c522a716-55a4-584d-a12e-ab135b4c08eb") + (sheetname "serial-carrier") + (sheetfile "serial-carrier.kicad_sch") + (attr through_hole) + (duplicate_pad_numbers_are_jumpers no) + (fp_line + (start 0.13 3.35) + (end 0.13 1.15) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "39a742ab-4817-43ba-b59e-fec67365543c") + ) + (fp_line + (start 0.75 -0.87) + (end 5.75 -0.87) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "57a7ae1f-aa3f-4d40-9de3-e769baa28284") + ) + (fp_line + (start 0.75 5.37) + (end 5.75 5.37) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid 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+ (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (net "/BTN_SELECT") + (pintype "passive") + (uuid "0398530b-79dc-45b1-886c-51343182e1d3") + ) + (pad "2" thru_hole circle + (at 0 4.5) + (size 1.7 1.7) + (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (net "/GND") + (pintype "passive") + (uuid "970e56ae-cc93-46cd-8807-ccc9cf082aa1") + ) + (pad "2" thru_hole circle + (at 6.5 4.5) + (size 1.7 1.7) + (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (net "/GND") + (pintype "passive") + (uuid "2f44f580-c7e4-4f03-ba46-49605735875c") + ) + (embedded_fonts no) + (model "${KICAD10_3DMODEL_DIR}/Button_Switch_THT.3dshapes/SW_TH_Tactile_Omron_B3F-100x.step" + (offset + (xyz 0 0 0) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 0 0 0) + ) + ) + ) + (footprint "MountingHole:MountingHole_3.2mm_M3" + (layer "F.Cu") + (uuid "1a8b4cef-8dea-4172-b360-f297696eb7e7") + (at 103.5 103.5) + (descr "Mounting Hole 3.2mm, M3, no annular, generated by kicad-footprint-generator mountinghole.py") + (tags "mountinghole M3") + (property "Reference" "H1" + (at 0 -4.15 0) + (layer "F.SilkS") + (hide yes) + (uuid "942249d7-2892-4702-9e47-3aa975dee74b") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "M3 mounting proposal / 3.2mm" + (at 0 4.15 0) + (layer "F.Fab") + (hide yes) + (uuid "293f6764-7211-46e3-a49c-3565059c6144") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "7a11fc8e-2d4b-4615-a09a-cc51d3fcaf24") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "50c8eef0-6de1-468a-a132-a389bf146f8f") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "KiLib_Generator" "mounting_hardware/mounting_hole" + (at 0 0 0) + (layer "F.SilkS") + (hide yes) + (uuid "36b2d4bf-e031-481a-96de-8e66cdad8c0b") + (effects + (font + (size 1 1) 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connector fit: 1.70 mm pads / 1.00 mm drills from installed KiCad PinHeader_1x04_P2.54mm_Vertical, awaiting selected actual pin/socket datasheet") + (tags "module provisional THT") + (property "Reference" "U1" + (at 12.7 21 0) + (layer "F.SilkS") + (uuid "4da63730-ca2f-4711-ac7d-31a41e5bab7d") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "HW678 / S3-N16R8" + (at 12.7 57 0) + (layer "F.Fab") + (hide yes) + (uuid "1f3098b2-20e5-42d0-82a3-fdd16eea3f58") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "6d045f0e-8c57-4970-ad19-218e6a6da564") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "bae61151-c60a-499e-97ad-06ebdf637ac9") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Status" "Header geometry nominal; outline/antenna clearance pending" + (at 0 0 0) + (layer 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(uuid "2c8cc7c5-7b73-4bc2-a384-b3a5ac459c92") + ) + (pad "3" thru_hole circle + (at 0 5.08) + (size 1.7 1.7) + (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (net "unconnected-(U1-EN-Pad3)") + (pinfunction "EN_3") + (pintype "input+no_connect") + (uuid "3d92a22d-6120-42f5-a02c-ee31eafb8eed") + ) + (pad "4" thru_hole circle + (at 0 7.62) + (size 1.7 1.7) + (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (net "/RS_DCD") + (pinfunction "GPIO4_4") + (pintype "input") + (uuid "d9f0d2af-a701-43e9-9d1e-58a6c7cb5250") + ) + (pad "5" thru_hole circle + (at 0 10.16) + (size 1.7 1.7) + (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (net "/RS_DSR") + (pinfunction "GPIO5_5") + (pintype "input") + (uuid "0ceca603-53a8-4a53-85cc-f7f8e7be90e4") + ) + (pad "6" thru_hole circle + (at 0 12.7) + (size 1.7 1.7) + (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (net "/RS_RI") + (pinfunction "GPIO6_6") + (pintype "input") + (uuid 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"netclass_patterns": [ + { "netclass": "Power", "pattern": "/+3V3" }, + { "netclass": "Power", "pattern": "/GND" } + ] + }, + "pcbnew": { + "last_paths": { + "idf": "", + "netlist": "", + "plot": "", + "specctra_dsn": "", + "step": "", + "vrml": "" + }, + "page_layout_descr_file": "" + }, + "schematic": { + "bus_aliases": {}, + "legacy_lib_dir": "", + "legacy_lib_list": [], + "top_level_sheets": [ + { + "filename": "serial-carrier.kicad_sch", + "name": "serial-carrier", + "uuid": "00000000-0000-0000-0000-000000000000" + } + ] + }, + "sheets": [], + "text_variables": {}, + "tuning_profiles": { + "meta": { + "version": 0 + }, + "tuning_profiles_impedance_geometric": [] + } +} diff --git a/hardware/PCB/serial-carrier.kicad_sch b/hardware/PCB/serial-carrier.kicad_sch new file mode 100644 index 0000000..46f7f73 --- /dev/null +++ b/hardware/PCB/serial-carrier.kicad_sch @@ -0,0 +1,400 @@ +(kicad_sch (version 20250114) (generator "eeschema") (uuid "c86e0d56-4290-5f2b-b790-14926c8cdeea") (paper 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0.125 W; exact resistor MPN pending" (at 327.66 160.02 0) (effects (font (size 1.27 1.27)) (hide yes))) +(pin "1" (uuid "d871ee2e-bc82-5f23-a436-7b7ab74b73a9")) +(pin "2" (uuid "96528b84-ba49-5f38-8445-b6ca2cadc93b")) +(instances (project "serial-carrier" (path "/c86e0d56-4290-5f2b-b790-14926c8cdeea" (reference "R3") (unit 1))))) +(wire (pts (xy 322.58 160.02) (xy 309.88 160.02)) (stroke (width 0) (type default)) (uuid "ad7355d6-b196-5b55-b518-28095d4cd010")) +(label "+3V3" (at 309.88 160.02 0) (effects (font (size 1.016 1.016)) (justify left bottom)) (uuid "08ba6112-d16a-5597-b3f3-8794ed1ea849")) +(wire (pts (xy 332.74 160.02) (xy 345.44 160.02)) (stroke (width 0) (type default)) (uuid "7a2af359-d23d-5777-9193-ff203ac538d8")) +(label "BTN_NEXT" (at 345.44 160.02 0) (effects (font (size 1.016 1.016)) (justify left bottom)) (uuid "5011a121-e49f-5298-8cc1-2998dfa40f7d")) +(symbol (lib_id "Carrier:SW_NO") (at 327.66 175.26 0) (unit 1) (in_bom yes) (on_board yes) (dnp no) (uuid "35caa6bb-42a6-512c-848c-f1e4457aa97f") +(property "Reference" "SW3" (at 327.66 167.64 0) (effects (font (size 1.27 1.27)) )) +(property "Value" "B3F-1000" (at 327.66 170.18 0) (effects (font (size 1.27 1.27)) )) +(property "Footprint" "Button_Switch_THT:SW_TH_Tactile_Omron_B3F-100x" (at 327.66 175.26 0) (effects (font (size 1.27 1.27)) (hide yes))) +(property "Datasheet" "" (at 327.66 175.26 0) (effects (font (size 1.27 1.27)) (hide yes))) +(property "Manufacturer" "Omron" (at 327.66 175.26 0) (effects (font (size 1.27 1.27)) (hide yes))) +(property "MPN" "B3F-1000" (at 327.66 175.26 0) (effects (font (size 1.27 1.27)) (hide yes))) +(property "Function" "Next" (at 327.66 175.26 0) (effects (font (size 1.27 1.27)) (hide yes))) +(property "Procurement" "Live stock not verified" (at 327.66 175.26 0) (effects (font (size 1.27 1.27)) (hide yes))) +(pin "1" (uuid "85beb3b7-e16f-5450-ba94-5711245a7b25")) +(pin "2" (uuid "300c4196-eb91-5e58-a9aa-c84b8f7c4219")) +(instances (project "serial-carrier" (path "/c86e0d56-4290-5f2b-b790-14926c8cdeea" (reference "SW3") (unit 1))))) +(wire (pts (xy 322.58 175.26) (xy 309.88 175.26)) (stroke (width 0) (type default)) (uuid "899495f9-e27d-5c7f-9961-bda42dd5b5b5")) +(label "BTN_NEXT" (at 309.88 175.26 0) (effects (font (size 1.016 1.016)) (justify left bottom)) (uuid "4917cd5a-7d37-54f4-8139-7ae4739c44c4")) +(wire (pts (xy 332.74 175.26) (xy 345.44 175.26)) (stroke (width 0) (type default)) (uuid "f48c99dc-9974-5205-8a87-3b1278a4fdfd")) +(label "GND" (at 345.44 175.26 0) (effects (font (size 1.016 1.016)) (justify left bottom)) (uuid "3c7713ca-d8f2-53fd-8e98-6fd376e4570c")) +(text "Next" (at 302.26 181.61 0) (effects (font (size 1.016 1.016)) (justify left top)) (uuid "0db41e9e-455f-5007-82ee-b485aacda4c4")) +(text "MODULE CARRIER - INITIAL SCHEMATIC" (at 15.24 15.24 0) (effects (font (size 2.54 2.54)) (justify left top)) (uuid "81374533-4a9c-521b-8834-9fa30bb907b5")) +(text "Native KiCad 10 schematic. Named wire labels join matching nets on this sheet.\nRead hardware/PCB/README.md before layout or fabrication." (at 15.24 24.13 0) (effects (font (size 1.27 1.27)) (justify left top)) (uuid "d9d89d85-2a9c-5e76-bd60-48c81ac7f524")) +(text "U1: complete development board" (at 53.34 57.15 0) (effects (font (size 1.778 1.778)) (justify left top)) (uuid "320a8f4e-ff8b-5100-845b-dfe249b39a2e")) +(text "Antenna up / USB down: left row 1-22, right row 23-44.\nNC marks mean unused on carrier, not unused inside module." (at 53.34 64.77 0) (effects (font (size 1.016 1.016)) (justify left top)) (uuid "649df1fa-48c0-580d-aeb8-d019ffd0b61d")) +(text "U2: complete RS-232 breakout" (at 177.8 57.15 0) (effects (font (size 1.778 1.778)) (justify left top)) (uuid "5226007c-1904-547d-8ddb-008d14b83d51")) +(text "Male 6253 selected. Numbers from published 5988 female CAD.\nVERIFY male header before routing; no footprint assigned.\nDE-9 and charge pump are already on the module." (at 177.8 64.77 0) (effects (font (size 1.016 1.016)) (justify left top)) (uuid "9b62e7ca-695a-51af-bbbe-e7ee4ee45c08")) +(text "Controls: active-low, firmware-debounced" (at 292.1 57.15 0) (effects (font (size 1.778 1.778)) (justify left top)) (uuid "9d91985c-7375-5177-9a5e-8280e3bcaff6")) +(text "External 2.2k pull-ups: ~1.5 mA pressed at 3.3 V.\nChosen for B3F-1000 rated contact load; internal\npull-ups may remain enabled. Exact resistor MPN pending." (at 292.1 64.77 0) (effects (font (size 1.016 1.016)) (justify left top)) (uuid "b2dd72f5-86fc-5ce1-b09a-67a6fe9404d4")) +(text "DS1: front view GND / VCC / SCL / SDA" (at 177.8 128.27 0) (effects (font (size 1.524 1.524)) (justify left top)) (uuid "7b57748d-38ca-5712-97f9-bf6dab6dafaf")) +(text "Power at 3.3 V only. Verify on-module I2C pull-ups;\nexternal values intentionally not guessed." (at 177.8 165.1 0) (effects (font (size 1.016 1.016)) (justify left top)) (uuid "fb23ec11-40f8-56c7-b78b-0da2d40e4b72")) +(text "POWER / RECOVERY\nPower only through U1's existing USB ports. No carrier 5 V input.\nU1 regulator supplies +3V3; GND pins are common on the module.\nPin 1 +3V3 and pin 22 GND model the onboard supply for ERC.\nGPIO19/20 native USB and GPIO43/44 UART0 remain onboard.\nVerify USB power isolation before attaching two powered hosts.\nKeep both USB connectors and reset/boot buttons accessible." (at 15.24 185.42 0) (effects (font (size 1.27 1.27)) (justify left top)) (uuid "cadf6b77-e888-5f04-b4f6-3873114844ca")) +(text "RS-232 / ELECTRICAL LIMITS\nTX/RX and modem labels are at the ESP32 logic side.\nOFF_N is active low; GPIO9 must remain open-drain.\nBreakout provides its OFF pull-up. No galvanic isolation.\nNo carrier connection to raw RS-232 voltages.\nCarrier GND, USB GND and RS-232 signal ground are common.\nNever power OLED or MAX3243 logic from 5 V." (at 152.4 185.42 0) (effects (font (size 1.27 1.27)) (justify left top)) (uuid "0f7da388-3edb-5cc3-9937-13492397a221")) +(text "BEFORE PCB RELEASE\nVerify male breakout pin order/footprint.\nConfirm header/socket finished-hole requirements.\nComplete module courtyards and antenna clearance.\nVerify 3.3 V budget, OLED pull-ups and USB power path.\nChoose mounting hardware and confirm button stock.\nERC is not hardware or fabrication approval." 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b/hardware/PCB/validate_footprints.py new file mode 100644 index 0000000..30f970c --- /dev/null +++ b/hardware/PCB/validate_footprints.py @@ -0,0 +1,129 @@ +#!/usr/bin/env python3 +"""Read-only regression checks for the two provisional module footprints. + +Run with the system Python that provides KiCad's installed pcbnew binding: + /usr/bin/python3 -B hardware/PCB/validate_footprints.py + +Paths resolve relative to this script, independent of the working directory. +No board, reports, or footprint files are written. Passing checks do not establish +physical connector fit, electrical correctness, DRC, or fabrication readiness. +""" + +from collections import Counter +from pathlib import Path +import sys +import unittest + +try: + import pcbnew as k +except ImportError as exc: + raise SystemExit( + "KiCad pcbnew binding unavailable. Use the system Python associated with " + "your KiCad installation (on this machine: /usr/bin/python3)." + ) from exc + + +LIBRARY = Path(__file__).resolve().parent / "Carrier.pretty" + + +def xy(vector): + """Keep native integer coordinates so comparisons do not hide deviations.""" + return vector.x, vector.y + + +def mm(x, y): + return k.FromMM(x), k.FromMM(y) + + +class FootprintRegression(unittest.TestCase): + def load(self, name): + self.assertTrue((LIBRARY / (name + ".kicad_mod")).is_file(), name) + footprint = k.FootprintLoad(str(LIBRARY), name) + self.assertIsNotNone(footprint, f"KiCad could not parse {name}") + self.assertEqual(footprint.GetValue(), name) + self.assertEqual(footprint.GetLayer(), k.F_Cu) + self.assertIn("PROVISIONAL connector fit", footprint.GetLibDescription()) + self.assertEqual(len(list(footprint.Zones())), 0, "Unexpected zone/keepout") + self.assertEqual(len(list(footprint.Models())), 0, "Unexpected 3D envelope") + graphics = list(footprint.GraphicalItems()) + for item in graphics: + self.assertNotIn(item.GetLayer(), (k.F_CrtYd, k.B_CrtYd, k.Edge_Cuts)) + self.assertIsInstance(item, (k.PCB_TEXT, k.PCB_SHAPE), + "Unexpected graphic/envelope type") + self.assertTrue(any(isinstance(item, k.PCB_TEXT) + and item.GetText() == "PROVISIONAL CONNECTOR FIT" + for item in graphics), "Missing visible provisional label") + return footprint + + def check_header(self, footprint, positions, hole_count=0): + pads = list(footprint.Pads()) + self.assertEqual(len(pads), len(positions) + hole_count) + numbered = [pad for pad in pads if pad.GetNumber()] + # Compare multiplicities so duplicate numbers cannot hide missing pads. + self.assertEqual(Counter(p.GetNumber() for p in numbered), + Counter({str(n): 1 for n in positions})) + for pad in numbered: + number = int(pad.GetNumber()) + with self.subTest(pad=number): + self.assertEqual(xy(pad.GetPosition()), mm(*positions[number])) + self.assertEqual(xy(pad.GetSize()), mm(1.7, 1.7)) + self.assertEqual(xy(pad.GetDrillSize()), mm(1, 1)) + self.assertEqual(pad.GetDrillShape(), k.PAD_DRILL_SHAPE_CIRCLE) + self.assertEqual(pad.GetAttribute(), k.PAD_ATTRIB_PTH) + self.assertEqual(pad.GetShape(), + k.PAD_SHAPE_RECT if number == 1 else k.PAD_SHAPE_CIRCLE) + self.assertEqual(pad.GetNetCode(), 0, "Unexpected assigned net") + for layer in (k.F_Cu, k.B_Cu, k.F_Mask, k.B_Mask): + self.assertTrue(pad.IsOnLayer(layer), "Missing copper/mask layer") + for layer in (k.F_Paste, k.B_Paste): + self.assertFalse(pad.IsOnLayer(layer), "Unexpected paste layer") + return [pad for pad in pads if not pad.GetNumber()] + + def test_oled(self): + footprint = self.load("OLED_26mm_I2C_Provisional") + positions = {n: (x, 1.5) for n, x in + enumerate((9.19, 11.73, 14.27, 16.81), 1)} + holes = self.check_header(footprint, positions, hole_count=4) + self.assertEqual(Counter(xy(p.GetPosition()) for p in holes), + Counter(mm(x, y) for x, y in ( + (1.75, 1.75), (24.25, 1.75), + (1.75, 24.25), (24.25, 24.25)))) + for pad in holes: + with self.subTest(hole=xy(pad.GetPosition())): + self.assertEqual(pad.GetAttribute(), k.PAD_ATTRIB_NPTH) + self.assertEqual(pad.GetShape(), k.PAD_SHAPE_CIRCLE) + self.assertEqual(pad.GetDrillShape(), k.PAD_DRILL_SHAPE_CIRCLE) + self.assertEqual(xy(pad.GetSize()), mm(2, 2)) + self.assertEqual(xy(pad.GetDrillSize()), mm(2, 2)) + self.assertEqual(pad.GetNetCode(), 0) + shapes = [g for g in footprint.GraphicalItems() if isinstance(g, k.PCB_SHAPE)] + self.assertEqual(len(shapes), 2, "Only board/display rectangles are verified") + self.assertEqual(Counter((xy(g.GetStart()), xy(g.GetEnd())) for g in shapes), + Counter([(mm(0, 0), mm(26, 26)), + (mm(1, 4.5), mm(25.5, 21))])) + for shape in shapes: + self.assertEqual(shape.GetShape(), k.SHAPE_T_RECT) + self.assertEqual(shape.GetLayer(), k.F_Fab) + self.assertEqual(shape.GetWidth(), k.FromMM(0.1)) + self.assertFalse(shape.IsAnyFill()) + # Stroke styles are not checked: this binding returns opaque LINE_STYLE + # pointers, so comparing GetLineStyle() results would compare identities, + # not the solid/dash values, and also emits SWIG leak warnings. + + def test_hw678(self): + footprint = self.load("HW678_2x22_Provisional") + positions = { + row * 22 + index + 1: (x, round(index * 2.54, 2)) + for row, x in enumerate((0, 25.4)) for index in range(22) + } + self.check_header(footprint, positions) + self.assertFalse(any(isinstance(g, k.PCB_SHAPE) + for g in footprint.GraphicalItems()), + "HW678 must not acquire guessed outlines or envelopes") + + +if __name__ == "__main__": + print(f"KiCad {k.GetBuildVersion()}; library: {LIBRARY}", flush=True) + suite = unittest.defaultTestLoader.loadTestsFromTestCase(FootprintRegression) + result = unittest.TextTestRunner(verbosity=2).run(suite) + sys.exit(0 if result.wasSuccessful() else 1) diff --git a/hardware/PCB/validate_pcb_draft.py b/hardware/PCB/validate_pcb_draft.py new file mode 100644 index 0000000..fa0a98a --- /dev/null +++ b/hardware/PCB/validate_pcb_draft.py @@ -0,0 +1,94 @@ +#!/usr/bin/env python3 +"""Read-only PCB checks and fresh KiCad reports; does not regenerate or save PCB. + +Requires KiCad's pcbnew binding in system Python. The known U2 footprint parity +warning is reported explicitly, not hidden or added to KiCad's exclusions. +""" +import json +from pathlib import Path +import subprocess +import xml.etree.ElementTree as ET +import pcbnew as p + +ROOT=Path(__file__).resolve().parent +PCB=ROOT/"serial-carrier.kicad_pcb" +OUT=ROOT/"validation" + +def run(*args): + subprocess.run(args,check=True,cwd=ROOT) + +run("kicad-cli","sch","export","netlist","--format","kicadxml","-o",str(OUT/"pcb-source-netlist.xml"),str(ROOT/"serial-carrier.kicad_sch")) +run("kicad-cli","pcb","drc","--format","json","--all-track-errors","--severity-all","--schematic-parity","-o",str(OUT/"pcb-parity-drc.json"),str(PCB)) +board=p.LoadBoard(str(PCB)) +source=ET.parse(OUT/"pcb-source-netlist.xml").getroot() +comps={c.get("ref"):c for c in source.findall("components/comp")} +footprints={f.GetReference():f for f in board.GetFootprints()} +assert set(footprints)==set(comps)|{"H1","H2","H3","H4"} +assert board.GetCopperLayerCount()==2 +assert p.ToMM(board.GetDesignSettings().GetBoardThickness())==1.6 +outline=[d for d in board.GetDrawings() if d.GetLayer()==p.Edge_Cuts] +assert len(outline)==6 +points={(round(p.ToMM(v.x)-100,5),round(p.ToMM(v.y)-100,5)) for d in outline for v in (d.GetStart(),d.GetEnd())} +assert points=={(0,0),(82,0),(82,80),(36,80),(36,61),(0,61)} +assert max(x for x,y in points)-min(x for x,y in points)==82 +assert max(y for x,y in points)-min(y for x,y in points)==80 +padnets={} +for net in source.findall("nets/net"): + for node in net.findall("node"): + padnets[(node.get("ref"),node.get("pin"))]=net.get("name") +seen=set() +for ref,comp in comps.items(): + fp=footprints[ref] + assert fp.GetValue()==comp.findtext("value"),ref + assert fp.GetPath().AsString().endswith("/"+comp.findtext("tstamps")),ref + wanted=comp.findtext("footprint") + if ref=="U2": + assert not wanted + assert fp.GetFPIDAsString()=="Carrier:MAX3243_Reference_Provisional" + else: + assert fp.GetFPIDAsString()==wanted,ref + for pad in fp.Pads(): + if not pad.GetNumber(): + continue + key=ref,pad.GetNumber() + assert pad.GetNetname()==padnets[key],(key,pad.GetNetname(),padnets[key]) + seen.add(key) +assert seen==set(padnets),"Missing or extra electrical pads" +for ref in ("H1","H2","H3","H4"): + assert footprints[ref].IsBoardOnly() + pads=list(footprints[ref].Pads()) + assert len(pads)==1 and pads[0].GetDrillSize().x==p.FromMM(3.2) + assert pads[0].GetAttribute()==p.PAD_ATTRIB_NPTH +tracks=list(board.GetTracks()) +assert tracks,"Draft unexpectedly unrouted" +for track in tracks: + if isinstance(track,p.PCB_VIA): + assert track.GetDrillValue()==p.FromMM(0.3) + assert track.GetWidth(p.F_Cu)==p.FromMM(0.7) + else: + assert track.GetLayer() in (p.F_Cu,p.B_Cu) + expected=0.5 if track.GetNetname() in ("/+3V3","/GND") else 0.25 + assert track.GetWidth()==p.FromMM(expected) +report=json.loads((OUT/"pcb-parity-drc.json").read_text()) +assert not report["violations"],report["violations"] +assert not report["unconnected_items"],report["unconnected_items"] +parity=report["schematic_parity"] +assert len(parity)==1 and parity[0]["type"]=="footprint_symbol_mismatch",parity +assert len(parity[0]["items"])==1 and parity[0]["items"][0]["uuid"]==footprints["U2"].m_Uuid.AsString() +summary={ + "carrier_bounds_mm":[82,80], + "copper_layers":2, + "draft_thickness_mm":1.6, + "electrical_footprints":len(comps), + "proposed_M3_mounts":4, + "physical_DRC_violations":0, + "unconnected_items":0, + "schematic_pad_nets_match":True, + "known_parity_warning":"U2 provisional female-reference footprint assigned on PCB only; schematic footprint intentionally blank", + "ignored_DRC_checks":report["ignored_checks"], + "not_validated":["male module pin map/fit", "assembly envelope and heights", "header/socket fit", "RF performance and antenna clearance", "power/return-path integrity", "USB power path", "OLED pull-ups", "fabrication process", "hardware operation"], +} +(OUT/"pcb-validation-summary.json").write_text(json.dumps(summary,indent=2)+"\n") +print("PCB draft verified: 82 x 80 mm; 2 copper layers; 0 physical DRC violations; 0 unrouted.") +print("All schematic pad nets match. One expected U2 footprint parity warning remains visible.") +print("Not fabrication-ready; see pcb-draft-notes.md and ignored checks in the DRC report.") diff --git a/hardware/PCB/validate_schematic.py b/hardware/PCB/validate_schematic.py new file mode 100644 index 0000000..f5e6899 --- /dev/null +++ b/hardware/PCB/validate_schematic.py @@ -0,0 +1,94 @@ +#!/usr/bin/env python3 +"""Export and validate the checked-in schematic; never regenerates the design.""" +import json +from pathlib import Path +import re +import subprocess +import xml.etree.ElementTree as ET + +ROOT = Path(__file__).resolve().parent +OUT = ROOT / "validation" +SCHEMATIC = ROOT / "serial-carrier.kicad_sch" + +def run(*args): + subprocess.run(args, check=True, cwd=ROOT) + +run("kicad-cli", "sch", "export", "netlist", "--format", "kicadxml", "-o", str(OUT / "serial-carrier.xml"), str(SCHEMATIC)) +run("kicad-cli", "sch", "erc", "--format", "json", "--exit-code-violations", "-o", str(OUT / "erc.json"), str(SCHEMATIC)) +root = ET.parse(OUT / "serial-carrier.xml").getroot() +nets = {net.get("name").removeprefix("/"): net.findall("node") for net in root.findall("nets/net")} +members = {name: sorted((node.get("ref"), node.get("pin")) for node in nodes) for name, nodes in nets.items()} +components = {comp.get("ref"): comp for comp in root.findall("components/comp")} +assert set(components) == {"U1", "U2", "DS1", "SW1", "SW2", "SW3", "R1", "R2", "R3"} + +# Independent firmware-to-module contract, not imported from the schematic generator. +contracts = [ + ("RS_TX", "RS232_TX_GPIO", "TX", "5"), + ("RS_RX", "RS232_RX_GPIO", "RX", "4"), + ("RS_RTS", "RS232_RTS_GPIO", "RTS", "8"), + ("RS_CTS", "RS232_CTS_GPIO", "CTS", "9"), + ("RS_DTR", "RS232_DTR_GPIO", "DTR", "6"), + ("RS_DSR", "RS232_DSR_GPIO", "DSR", "7"), + ("RS_DCD", "RS232_DCD_GPIO", "DCD", "3"), + ("RS_RI", "RS232_RI_GPIO", "RI", "10"), + ("RS_VALID", "RS232_VALID_GPIO", "VLD", "11"), + ("RS_OFF_N", "RS232_FORCE_OFF_N_GPIO", "OFF_N", "12"), + ("OLED_SDA", "LOCAL_UI_DISPLAY_SDA_GPIO", "SDA", "4"), + ("OLED_SCL", "LOCAL_UI_DISPLAY_SCL_GPIO", "SCL", "3"), + ("BTN_PREVIOUS", "LOCAL_UI_BUTTON_PREVIOUS_GPIO", None, None), + ("BTN_SELECT", "LOCAL_UI_BUTTON_SELECT_GPIO", None, None), + ("BTN_NEXT", "LOCAL_UI_BUTTON_NEXT_GPIO", None, None), +] +firmware = ROOT.parents[1].joinpath("src/board_pins.h").read_text() +for net, macro, peripheral_name, peripheral_pin in contracts: + match = re.search(r"^#define\s+" + re.escape(macro) + r"\s+GPIO_NUM_(\d+)\s*$", firmware, re.MULTILINE) + assert match, macro + gpio = "GPIO" + match.group(1) + mcu = [node for node in nets[net] if node.get("ref") == "U1"] + assert len(mcu) == 1 and mcu[0].get("pinfunction") == gpio + "_" + mcu[0].get("pin"), (net, gpio) + if peripheral_name: + ref = "DS1" if net.startswith("OLED_") else "U2" + node = [node for node in nets[net] if node.get("ref") == ref] + assert len(node) == 1 and node[0].get("pin") == peripheral_pin + assert node[0].get("pinfunction") == peripheral_name + "_" + peripheral_pin + assert len(nets[net]) == 2, (net, members[net]) + +for i, net in enumerate(("BTN_PREVIOUS", "BTN_SELECT", "BTN_NEXT"), 1): + assert len(nets[net]) == 3 + assert (f"SW{i}", "1") in members[net] and (f"R{i}", "2") in members[net] + assert components[f"SW{i}"].findtext("value") == "B3F-1000" + assert components[f"R{i}"].findtext("value") == "2.2k 1%" +assert members["+3V3"] == sorted([("U1","1"),("U1","2"),("U2","1"),("DS1","2"),("R1","1"),("R2","1"),("R3","1")]) +assert members["GND"] == sorted([("U1","22"),("U1","23"),("U1","43"),("U1","44"),("U2","2"),("DS1","1"),("SW1","2"),("SW2","2"),("SW3","2")]) +active = {name for name in nets if not name.startswith("unconnected-")} +assert active == {"+3V3", "GND"} | {row[0] for row in contracts} +for name, nodes in nets.items(): + if name.startswith("unconnected-"): + assert len(nodes) == 1 and nodes[0].get("ref") == "U1" +# All 44 MCU header pins must occur exactly once, including deliberate no-connects. +assert sorted(int(node.get("pin")) for nodes in nets.values() for node in nodes if node.get("ref") == "U1") == list(range(1,45)) +# USB/UART0, 5 V and PSRAM-conflicting pins must never be carrier nets. +for name in active: + assert not any(node.get("ref") == "U1" and node.get("pin") in ("21","24","25","33","34","35","41","42") for node in nets[name]) +# U2's physical male footprint must stay explicitly unresolved in this draft. +assert not components["U2"].findtext("footprint") +expected = json.loads((OUT / "expected-nets.json").read_text()) +assert set(expected) == active +for net, nodes in expected.items(): + assert members[net] == sorted(tuple(node) for node in nodes), net +report = json.loads((OUT / "erc.json").read_text()) +assert not any(sheet["violations"] for sheet in report["sheets"]) +run("kicad-cli", "sch", "export", "pdf", "-o", str(ROOT / "serial-carrier.pdf"), str(SCHEMATIC)) +run("kicad-cli", "sch", "export", "svg", "-o", str(OUT) + "/", str(SCHEMATIC)) +summary = "\n".join([ + "Native schematic validation passed.", + "KiCad ERC: zero reported errors/warnings; no project exclusions added.", + "17 connected nets, 9 components; exact net memberships verified.", + "15 firmware GPIO definitions independently checked against exported pin functions.", + "All 44 MCU header pins accounted for; USB/UART0/5V/PSRAM pins unused on carrier.", + "PDF and SVG exported successfully.", + "Not validated: male-module physical mapping, power budget/path, OLED pull-ups,", + "selected connector fit, PCB DRC/layout, procurement, or assembled hardware.", +]) + "\n" +(OUT / "summary.txt").write_text(summary) +print(summary) diff --git a/hardware/PCB/validation/erc.json b/hardware/PCB/validation/erc.json new file mode 100644 index 0000000..bf6dc20 --- /dev/null +++ b/hardware/PCB/validation/erc.json @@ -0,0 +1,36 @@ +{ + "$schema": "https://schemas.kicad.org/erc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-20T20:14:47", + "ignored_checks": [ + { + "description": "Global label only appears once in the schematic", + "key": "single_global_label" + }, + { + "description": "Four connection points are joined together", + "key": "four_way_junction" + }, + { + "description": "SPICE model issue", + "key": "simulation_model_issue" + }, + { + "description": "Assigned footprint doesn't match footprint filters", + "key": "footprint_filter" + } + ], + "included_severities": [ + "error", + "warning" + ], + "kicad_version": "10.0.6", + "sheets": [ + { + "path": "/", + "uuid_path": "/c86e0d56-4290-5f2b-b790-14926c8cdeea", + "violations": [] + } + ], + "source": "serial-carrier.kicad_sch" +} diff --git a/hardware/PCB/validation/expected-nets.json b/hardware/PCB/validation/expected-nets.json new file mode 100644 index 0000000..d7c8dd5 --- /dev/null +++ b/hardware/PCB/validation/expected-nets.json @@ -0,0 +1,232 @@ +{ + "+3V3": [ + [ + "U1", + "1" + ], + [ + "U1", + "2" + ], + [ + "U2", + "1" + ], + [ + "DS1", + "2" + ], + [ + "R1", + "1" + ], + [ + "R2", + "1" + ], + [ + "R3", + "1" + ] + ], + "BTN_NEXT": [ + [ + "U1", + "20" + ], + [ + "R3", + "2" + ], + [ + "SW3", + "1" + ] + ], + "BTN_PREVIOUS": [ + [ + "U1", + "16" + ], + [ + "R1", + "2" + ], + [ + "SW1", + "1" + ] + ], + "BTN_SELECT": [ + [ + "U1", + "19" + ], + [ + "R2", + "2" + ], + [ + "SW2", + "1" + ] + ], + "GND": [ + [ + "U1", + "22" + ], + [ + "U1", + "23" + ], + [ + "U1", + "43" + ], + [ + "U1", + "44" + ], + [ + "U2", + "2" + ], + [ + "DS1", + "1" + ], + [ + "SW1", + "2" + ], + [ + "SW2", + "2" + ], + [ + "SW3", + "2" + ] + ], + "OLED_SCL": [ + [ + "U1", + "18" + ], + [ + "DS1", + "3" + ] + ], + "OLED_SDA": [ + [ + "U1", + "17" + ], + [ + "DS1", + "4" + ] + ], + "RS_CTS": [ + [ + "U1", + "9" + ], + [ + "U2", + "9" + ] + ], + "RS_DCD": [ + [ + "U1", + "4" + ], + [ + "U2", + "3" + ] + ], + "RS_DSR": [ + [ + "U1", + "5" + ], + [ + "U2", + "7" + ] + ], + "RS_DTR": [ + [ + "U1", + "7" + ], + [ + "U2", + "6" + ] + ], + "RS_OFF_N": [ + [ + "U1", + "15" + ], + [ + "U2", + "12" + ] + ], + "RS_RI": [ + [ + "U1", + "6" + ], + [ + "U2", + "10" + ] + ], + "RS_RTS": [ + [ + "U1", + "8" + ], + [ + "U2", + "8" + ] + ], + "RS_RX": [ + [ + "U1", + "11" + ], + [ + "U2", + "4" + ] + ], + "RS_TX": [ + [ + "U1", + "10" + ], + [ + "U2", + "5" + ] + ], + "RS_VALID": [ + [ + "U1", + "12" + ], + [ + "U2", + "11" + ] + ] +} diff --git a/hardware/PCB/validation/pcb-draft-3d.png b/hardware/PCB/validation/pcb-draft-3d.png new file mode 100644 index 0000000000000000000000000000000000000000..d6e58f8ab418f1cf2fdec932a989a5103b843c07 GIT binary patch literal 97814 zcmb4rbyQT}*Y^M-0*as#(t-$r2#82Ch=hOwN_R;}igbh0sS?sD-Q5F{A|*962uL>! z&CI;#`u+ai=Xsxh-u1ZFEN9(0_uLcv?ETrF&%OjJDac$Sq9%gDVAo`yOTLD|@C{(F zOL12&gDWXd-_U{oF4;@Ss$2p8Jg&S6g25PJvXW0#T#`0typwbsJ-IOa@iTpqEQxRK z6cWO(GF?uWXl44+UfuE%=jpyRHOH%~+5XkD6vaheT(dXi9^TsQnANlXu3ca-7&J4q zJVZ=%H#@CJvY?RAfb`O1Cep8dGoMQRtm6J)%HnGq>`k3bolIA{#8M->MBczxdIeLH zlW6Vr4#als$B&z_7rtP8Fj(53dn#_Yf4?5e!HA(RO80Ozp#Oayy%k8qdjNeE*Ua_7 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no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [ + { + "description": "Carrier:MAX3243_Reference_Provisional stimmt nicht mit dem Footprint des Symbols () überein.", + "items": [ + { + "description": "Footprint U2", + "pos": { + "x": 143.0, + "y": 130.0 + }, + "uuid": "812387f6-6524-459e-8102-fe9c55122668" + } + ], + "severity": "warning", + "type": "footprint_symbol_mismatch" + } + ], + "source": "serial-carrier.kicad_pcb", + "unconnected_items": [], + "violations": [] +} diff --git a/hardware/PCB/validation/pcb-routing-all-drc.json b/hardware/PCB/validation/pcb-routing-all-drc.json new file mode 100644 index 0000000..838eab3 --- /dev/null +++ b/hardware/PCB/validation/pcb-routing-all-drc.json @@ -0,0 +1,37 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-20T22:50:33", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "serial-carrier.kicad_pcb", + "unconnected_items": [], + "violations": [] +} diff --git a/hardware/PCB/validation/pcb-routing-baseline.json b/hardware/PCB/validation/pcb-routing-baseline.json new file mode 100644 index 0000000..3823582 --- /dev/null +++ b/hardware/PCB/validation/pcb-routing-baseline.json @@ -0,0 +1,911 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-20T22:39:18", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "serial-carrier.kicad_pcb", + "unconnected_items": [ + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 19 [/BTN_SELECT] von U1", + "pos": { + "x": 108.0, + "y": 149.72 + }, + "uuid": "f7b9badd-1db5-4575-9da8-979a7c8f3946" + }, + { + "description": "Durchsteckpad 1 [/BTN_SELECT] von SW2", + "pos": { + "x": 155.0, + "y": 168.0 + }, + "uuid": "574d93e4-d3fc-4c28-b2d5-4e7d8682c22f" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 1 [/BTN_SELECT] von SW2", + "pos": { + "x": 155.0, + "y": 168.0 + }, + "uuid": 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"severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 6 [/RS_RI] von U1", + "pos": { + "x": 108.0, + "y": 116.7 + }, + "uuid": "f35f1696-b778-437b-8cce-67b8c4d5f5d0" + }, + { + "description": "Durchsteckpad 10 [/RS_RI] von U2", + "pos": { + "x": 165.86, + "y": 130.0 + }, + "uuid": "e28de6f2-fb85-4849-ba1a-e98e2a231492" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 7 [/RS_DTR] von U1", + "pos": { + "x": 108.0, + "y": 119.24 + }, + "uuid": "354ab122-85b1-4c9c-9385-d5091fe12303" + }, + { + "description": "Durchsteckpad 6 [/RS_DTR] von U2", + "pos": { + "x": 155.7, + "y": 130.0 + }, + "uuid": "81e8ad67-4bdc-4f57-90b1-68cff6a95261" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 8 [/RS_RTS] von U1", + "pos": { + "x": 108.0, + "y": 121.78 + }, + "uuid": "55162730-46fd-465d-a1c5-20aed09ed534" + }, + { + "description": "Durchsteckpad 8 [/RS_RTS] von U2", + "pos": { + "x": 160.78, + "y": 130.0 + }, + "uuid": "5c304724-2bc6-409d-9c59-2e40adc557b9" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 9 [/RS_CTS] von U1", + "pos": { + "x": 108.0, + "y": 124.32 + }, + "uuid": "f75c20f8-d3b5-4c3b-9919-cb044b2da5c3" + }, + { + "description": "Durchsteckpad 9 [/RS_CTS] von U2", + "pos": { + "x": 163.32, + "y": 130.0 + }, + "uuid": "a8411036-6859-4041-84b8-2c80c326c58e" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 10 [/RS_TX] von U1", + "pos": { + "x": 108.0, + "y": 126.86 + }, + "uuid": "22c323db-7146-44af-951b-04a1d7dbb2fe" + }, + { + "description": "Durchsteckpad 5 [/RS_TX] von U2", + "pos": { + "x": 153.16, + "y": 130.0 + }, + "uuid": "f919098b-4ad7-4600-9e8b-3375a1cff050" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 11 [/RS_RX] von U1", + "pos": { + "x": 108.0, + "y": 129.4 + }, + "uuid": "6573852d-5714-4c8d-8793-0be87f5a052a" + }, + { + "description": "Durchsteckpad 4 [/RS_RX] von U2", + "pos": { + "x": 150.62, + "y": 130.0 + }, + "uuid": "3d90cce4-14d8-46a0-b560-09524f11698f" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 12 [/RS_VALID] von U1", + "pos": { + "x": 108.0, + "y": 131.94 + }, + "uuid": "2fbc596b-c88f-4fc6-aa94-5dad4fcac9cc" + }, + { + "description": "Durchsteckpad 11 [/RS_VALID] von U2", + "pos": { + "x": 168.4, + "y": 130.0 + }, + "uuid": "9ad42f44-160f-4aa5-bcf0-a4466c090438" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 15 [/RS_OFF_N] von U1", + "pos": { + "x": 108.0, + "y": 139.56 + }, + "uuid": "34e1afe9-b3fc-4d3a-9e33-38b32244f19e" + }, + { + "description": "Durchsteckpad 12 [/RS_OFF_N] von U2", + "pos": { + "x": 170.94, + "y": 130.0 + }, + "uuid": "a43ba2f2-477d-4850-87de-e1591119d5ae" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 1 [/BTN_PREVIOUS] von SW1", + "pos": { + "x": 143.0, + "y": 168.0 + }, + "uuid": "5214c011-545b-4ae7-9cdb-852ade815805" + }, + { + "description": "Durchsteckpad 1 [/BTN_PREVIOUS] von SW1", + "pos": { + "x": 149.5, + "y": 168.0 + }, + "uuid": "84202d30-b2fe-4170-8146-69b68d3b82a1" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 1 [/BTN_PREVIOUS] von SW1", + "pos": { + "x": 149.5, + "y": 168.0 + }, + "uuid": "84202d30-b2fe-4170-8146-69b68d3b82a1" + }, + { + "description": "Durchsteckpad 2 [/BTN_PREVIOUS] von R1", + "pos": { + "x": 150.62, + "y": 134.0 + }, + "uuid": "8237f507-f5c7-4eb6-9aa1-f46af2981e7c" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 2 [/BTN_PREVIOUS] von R1", + "pos": { + "x": 150.62, + "y": 134.0 + }, + "uuid": "8237f507-f5c7-4eb6-9aa1-f46af2981e7c" + }, + { + "description": "Durchsteckpad 16 [/BTN_PREVIOUS] von U1", + "pos": { + "x": 108.0, + "y": 142.1 + }, + "uuid": "fc705960-92fa-4d8f-bb0e-ce2b82d1e7fc" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 17 [/OLED_SDA] von U1", + "pos": { + "x": 108.0, + "y": 144.64 + }, + "uuid": "1f91549c-5cb2-465f-86df-b2f1b0c16ed8" + }, + { + "description": "Durchsteckpad 4 [/OLED_SDA] von DS1", + "pos": { + "x": 159.81, + "y": 137.5 + }, + "uuid": "91a4dcef-1b36-4e3d-a15c-c4578077c27b" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 18 [/OLED_SCL] von U1", + "pos": { + "x": 108.0, + "y": 147.18 + }, + "uuid": "1c55fd03-0b3e-494f-a37b-6e0b3496cfc9" + }, + { + "description": "Durchsteckpad 3 [/OLED_SCL] von DS1", + "pos": { + "x": 157.27, + "y": 137.5 + }, + "uuid": "704668d0-88bf-4b51-840a-60a35804fafd" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 20 [/BTN_NEXT] von U1", + "pos": { + "x": 108.0, + "y": 152.26 + }, + "uuid": "e7159c90-4e8d-4b21-8e84-a7f59f793440" + }, + { + "description": "Durchsteckpad 1 [/BTN_NEXT] von SW3", + "pos": { + "x": 167.0, + "y": 168.0 + }, + "uuid": "c67d0b07-c47f-48b3-9e79-7aed82edbbfc" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 1 [/BTN_NEXT] von SW3", + "pos": { + "x": 167.0, + "y": 168.0 + }, + "uuid": "c67d0b07-c47f-48b3-9e79-7aed82edbbfc" + }, + { + "description": "Durchsteckpad 1 [/BTN_NEXT] von SW3", + "pos": { + "x": 173.5, + "y": 168.0 + }, + "uuid": "62f3da3b-8297-4232-92ee-88f3ce4a7d36" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 1 [/BTN_NEXT] von SW3", + "pos": { + "x": 173.5, + "y": 168.0 + }, + "uuid": "62f3da3b-8297-4232-92ee-88f3ce4a7d36" + }, + { + "description": "Durchsteckpad 2 [/BTN_NEXT] von R3", + "pos": { + "x": 172.62, + "y": 134.0 + }, + "uuid": "9e9dfe49-4b68-472b-a86c-bfcee913a81b" + } + ], + "severity": "error", + "type": "unconnected_items" + } + ], + "violations": [] +} diff --git a/hardware/PCB/validation/pcb-routing-check.json b/hardware/PCB/validation/pcb-routing-check.json new file mode 100644 index 0000000..4717313 --- /dev/null +++ b/hardware/PCB/validation/pcb-routing-check.json @@ -0,0 +1,85 @@ +{ + "immutable_geometry_nets_pads_linkage_preserved": true, + "board_sha256": "03b69c4084dba328b11e2373c219e8fe462bcb3add934cf9f527214b21bd9cb6", + "independent_min_different_net_or_npth_clearance_mm": 0.2749999999999886, + "closest_items": [ + "R2.2:c118f27f-8ad4-4abe-b9c0-a30a22fe60c9", + "99fb402a-445b-4eba-aedf-76b7f0cad042" + ], + "min_copper_or_npth_edge_gap_mm": 0.5250000000000057, + "min_rf_gap_mm": 0.025000000000005684, + "min_via_to_other_drilled_hole_gap_mm": 0.8401754250991242, + "track_width_counts": { + "0.25": 425, + "0.5": 144 + }, + "routed_length_mm_by_net": { + "/BTN_SELECT": 95.16152954766495, + "/GND": 152.2615364335217, + "/+3V3": 106.94219089103528, + "/RS_DCD": 47.76152984055992, + "/RS_DSR": 56.835284377834164, + "/RS_RI": 66.02000635033798, + "/RS_DTR": 52.162796381301995, + "/RS_RTS": 56.23655121147421, + "/RS_CTS": 58.073809511675655, + "/RS_TX": 47.51030692030297, + "/RS_RX": 43.90406233625865, + "/RS_VALID": 64.36573922778403, + "/RS_OFF_N": 67.05000417516253, + "/BTN_PREVIOUS": 86.95076506672746, + "/OLED_SDA": 54.781626385188304, + "/OLED_SCL": 53.30787155502609, + "/BTN_NEXT": 106.4266552277327 + }, + "tracks": 569, + "vias": 20, + "copper_zones": 0, + "drc_freshly_run": true, + "drc_violations": 0, + "unconnected_items": 0, + "drc_ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "overwrite_guard_tests": [ + { + "args": [ + "--route" + ], + "exit_code": 2, + "reason": "route_pcb_draft.py: error: --route requires --overwrite; back up manual routing first" + }, + { + "args": [ + "--route", + "--overwrite" + ], + "exit_code": 2, + "reason": "route_pcb_draft.py: error: existing routing protected; --replace-routes required even for preview" + }, + { + "args": [], + "exit_code": 2, + "reason": "route_pcb_draft.py: error: existing routing protected; --replace-routes required even for preview" + } + ] +} diff --git a/hardware/PCB/validation/pcb-routing-check.py b/hardware/PCB/validation/pcb-routing-check.py new file mode 100644 index 0000000..b904d8f --- /dev/null +++ b/hardware/PCB/validation/pcb-routing-check.py @@ -0,0 +1,122 @@ +#!/usr/bin/python3 +"""Read-only draft audit; needs pcbnew, numpy, shapely and kicad-cli. +Writes fresh DRC and audit JSON reports, never modifies the board. + +Independent continuous centreline/radius checks complement KiCad DRC. Restricted +here to the existing circle/axis-aligned rectangular THT pads and straight tracks. +""" +from collections import Counter +import hashlib +import importlib.util +import json +from pathlib import Path +import subprocess + +import pcbnew as p +from shapely.geometry import Point, LineString, Polygon, box + +ROOT = Path(__file__).resolve().parent.parent +spec = importlib.util.spec_from_file_location('router', ROOT / 'route_pcb_draft.py') +r = importlib.util.module_from_spec(spec) +spec.loader.exec_module(r) +board = p.LoadBoard(str(r.PCB)) +original = p.LoadBoard(str(ROOT / 'validation/pcb-routing-input.kicad_pcb')) +assert r.identity(board) == r.identity(original), 'immutable source geometry/linkage changed' +items, holes = [], [] +for f in board.GetFootprints(): + for pad in f.Pads(): + xy = r.pos(pad) + assert pad.GetOrientationDegrees() % 90 == 0 + assert pad.GetShape() in (p.PAD_SHAPE_CIRCLE, p.PAD_SHAPE_RECT) + if pad.GetShape() == p.PAD_SHAPE_CIRCLE: + assert pad.GetSize().x == pad.GetSize().y + geom, radius = Point(xy), p.ToMM(pad.GetSize().x) / 2 + else: + bb = pad.GetBoundingBox() + geom = box(p.ToMM(bb.GetX()), p.ToMM(bb.GetY()), + p.ToMM(bb.GetRight()), p.ToMM(bb.GetBottom())) + radius = 0 + label = f.GetReference() + '.' + pad.GetNumber() + ':' + pad.m_Uuid.AsString() + layers = {l for l in r.LAYERS if pad.IsOnLayer(l)} + items.append((label, pad.GetNetCode(), layers, geom, radius)) + if pad.GetDrillSize().x: + assert pad.GetDrillSize().x == pad.GetDrillSize().y + holes.append((label, Point(xy), p.ToMM(pad.GetDrillSize().x) / 2, False)) +track_lengths = Counter() +widths = Counter() +for t in board.GetTracks(): + is_via = isinstance(t, p.PCB_VIA) + if is_via: + geom, radius, layers = Point(r.pos(t)), p.ToMM(t.GetWidth(p.F_Cu)) / 2, set(r.LAYERS) + assert abs(radius - 0.35) < 1e-8 and t.GetDrillValue() == r.mm(0.3) + holes.append((t.m_Uuid.AsString(), geom, 0.15, True)) + else: + geom = LineString([(p.ToMM(t.GetStart().x), p.ToMM(t.GetStart().y)), + (p.ToMM(t.GetEnd().x), p.ToMM(t.GetEnd().y))]) + radius, layers = p.ToMM(t.GetWidth()) / 2, {t.GetLayer()} + expected = 0.5 if t.GetNetname() in ('/+3V3', '/GND') else 0.25 + assert abs(2 * radius - expected) < 1e-8 + widths[str(2 * radius)] += 1 + track_lengths[t.GetNetname()] += geom.length + items.append((t.m_Uuid.AsString(), t.GetNetCode(), layers, geom, radius)) + +min_clearance = float('inf') +closest = None +for i, a in enumerate(items): + for b in items[i + 1:]: + if not a[2].intersection(b[2]) or (a[1] and a[1] == b[1]): + continue + distance = a[3].distance(b[3]) - a[4] - b[4] + if distance < min_clearance: + min_clearance, closest = distance, (a[0], b[0]) +assert min_clearance >= 0.25 - 1e-6, (min_clearance, closest) +outline = Polygon([(100,100),(182,100),(182,180),(136,180),(136,161),(100,161)]) +rf = box(110, 100, 131, 113) +min_edge, min_rf = float('inf'), float('inf') +for label, net, layers, geom, radius in items: + assert outline.covers(geom), label + edge_gap = outline.boundary.distance(geom) - radius + rf_gap = rf.distance(geom) - radius + min_edge, min_rf = min(min_edge, edge_gap), min(min_rf, rf_gap) + assert edge_gap >= 0.5 - 1e-6, (label, edge_gap) + assert rf_gap > 0, (label, rf_gap) +min_via_hole_gap = float('inf') +for i, a in enumerate(holes): + for b in holes[i + 1:]: + if not (a[3] or b[3]): + continue + gap = a[1].distance(b[1]) - a[2] - b[2] + min_via_hole_gap = min(min_via_hole_gap, gap) + assert gap >= 0.25 - 1e-6, (a[0], b[0], gap) + +# Refusal paths must leave the routed board byte-for-byte unchanged. +before = r.PCB.read_bytes() +guards = [] +for args in (['--route'], ['--route', '--overwrite'], []): + result = subprocess.run(['/usr/bin/python3', '-B', str(ROOT/'route_pcb_draft.py'), *args], + capture_output=True, text=True, timeout=20) + assert result.returncode == 2, (args, result.stdout, result.stderr) + assert r.PCB.read_bytes() == before + guards.append({'args': args, 'exit_code': result.returncode, + 'reason': result.stderr.splitlines()[-1]}) +subprocess.run(['kicad-cli', 'pcb', 'drc', '--format', 'json', '--all-track-errors', + '--severity-all', '--exit-code-violations', '-o', + str(ROOT/'validation/pcb-routing-drc.json'), str(r.PCB)], + check=True, timeout=60) +assert r.PCB.read_bytes() == before, 'board changed during audit' +drc = json.loads(ROOT.joinpath('validation/pcb-routing-drc.json').read_text()) +assert not drc['violations'] and not drc['unconnected_items'] +report = dict(immutable_geometry_nets_pads_linkage_preserved=True, + board_sha256=hashlib.sha256(before).hexdigest(), + independent_min_different_net_or_npth_clearance_mm=min_clearance, + closest_items=closest, min_copper_or_npth_edge_gap_mm=min_edge, + min_rf_gap_mm=min_rf, min_via_to_other_drilled_hole_gap_mm=min_via_hole_gap, + track_width_counts=widths, routed_length_mm_by_net=track_lengths, + tracks=sum(not isinstance(t,p.PCB_VIA) for t in board.GetTracks()), + vias=sum(isinstance(t,p.PCB_VIA) for t in board.GetTracks()), + copper_zones=sum(not z.GetIsRuleArea() for z in board.Zones()), + drc_freshly_run=True, + drc_violations=len(drc['violations']), unconnected_items=len(drc['unconnected_items']), + drc_ignored_checks=drc['ignored_checks'], overwrite_guard_tests=guards) +ROOT.joinpath('validation/pcb-routing-check.json').write_text(json.dumps(report, indent=2)+'\n') +print(json.dumps(report, indent=2)) diff --git a/hardware/PCB/validation/pcb-routing-drc.json b/hardware/PCB/validation/pcb-routing-drc.json new file mode 100644 index 0000000..a989938 --- /dev/null +++ b/hardware/PCB/validation/pcb-routing-drc.json @@ -0,0 +1,37 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-20T23:07:33", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning", + "exclusion" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "serial-carrier.kicad_pcb", + "unconnected_items": [], + "violations": [] +} diff --git a/hardware/PCB/validation/pcb-routing-dry-run.log b/hardware/PCB/validation/pcb-routing-dry-run.log new file mode 100644 index 0000000..038ce82 --- /dev/null +++ b/hardware/PCB/validation/pcb-routing-dry-run.log @@ -0,0 +1,58 @@ +/builddir/build/BUILD/kicad-10.0.6-build/kicad-10.0.6/include/properties/property.h(607): assert "m_choices.GetCount() > 0" failed in PROPERTY_ENUM(): No enum choices defined +/builddir/build/BUILD/kicad-10.0.6-build/kicad-10.0.6/include/properties/property.h(607): assert "m_choices.GetCount() > 0" failed in PROPERTY_ENUM(): No enum choices defined +/builddir/build/BUILD/kicad-10.0.6-build/kicad-10.0.6/include/properties/property.h(607): assert "m_choices.GetCount() > 0" failed in PROPERTY_ENUM(): No enum choices defined +{"net": "/+3V3", "start": "U1.1", "end": "U1.2", "start_mm": [108.0, 104.0], "end_mm": [108.0, 106.54], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 52} +{"net": "/+3V3", "start": "R2.1", "end": "DS1.2", "start_mm": [154.0, 134.0], "end_mm": [154.73, 137.5], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 911} +{"net": "/+3V3", "start": "U2.1", "end": "R1.1", "start_mm": [143.0, 130.0], "end_mm": [143.0, 134.0], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 81} +{"net": "/BTN_NEXT", "start": "SW3.1", "end": "SW3.1", "start_mm": [167.0, 168.0], "end_mm": [173.5, 168.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 131} +{"net": "/BTN_PREVIOUS", "start": "SW1.1", "end": "SW1.1", "start_mm": [149.5, 168.0], "end_mm": [143.0, 168.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 131} +{"net": "/BTN_SELECT", "start": "SW2.1", "end": "SW2.1", "start_mm": [155.0, 168.0], "end_mm": [161.5, 168.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 131} +{"net": "/+3V3", "start": "DS1.2", "end": "R3.1", "start_mm": [154.73, 137.5], "end_mm": [165.0, 134.0], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 5139} +{"net": "/+3V3", "start": "R1.1", "end": "R2.1", "start_mm": [143.0, 134.0], "end_mm": [154.0, 134.0], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 14153} +{"net": "/BTN_SELECT", "start": "SW2.1", "end": "R2.2", "start_mm": [161.5, 168.0], "end_mm": [161.62, 134.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 2039} +{"net": "/BTN_NEXT", "start": "SW3.1", "end": "R3.2", "start_mm": [173.5, 168.0], "end_mm": [172.62, 134.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 12615} +{"net": "/BTN_PREVIOUS", "start": "R1.2", "end": "SW1.1", "start_mm": [150.62, 134.0], "end_mm": [149.5, 168.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 15179} +{"net": "/+3V3", "start": "U1.2", "end": "U2.1", "start_mm": [108.0, 106.54], "end_mm": [143.0, 130.0], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 894511} +{"net": "/RS_RX", "start": "U1.11", "end": "U2.4", "start_mm": [108.0, 129.4], "end_mm": [150.62, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 51516} +{"net": "/BTN_PREVIOUS", "start": "U1.16", "end": "R1.2", "start_mm": [108.0, 142.1], "end_mm": [150.62, 134.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 94479} +{"net": "/RS_DCD", "start": "U1.4", "end": "U2.3", "start_mm": [108.0, 111.62], "end_mm": [148.08, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 266031} +{"net": "/RS_TX", "start": "U1.10", "end": "U2.5", "start_mm": [108.0, 126.86], "end_mm": [153.16, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 175689} +{"net": "/RS_DTR", "start": "U1.7", "end": "U2.6", "start_mm": [108.0, 119.24], "end_mm": [155.7, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 326823} +{"net": "/OLED_SCL", "start": "U1.18", "end": "DS1.3", "start_mm": [108.0, 147.18], "end_mm": [157.27, 137.5], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 82557} +{"net": "/BTN_SELECT", "start": "SW2.1", "end": "U1.19", "start_mm": [155.0, 168.0], "end_mm": [108.0, 149.72], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 147997} +{"net": "/OLED_SDA", "start": "U1.17", "end": "DS1.4", "start_mm": [108.0, 144.64], "end_mm": [159.81, 137.5], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 266428} +{"net": "/RS_DSR", "start": "U1.5", "end": "U2.7", "start_mm": [108.0, 114.16], "end_mm": [158.24, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 372014} +{"net": "/RS_RTS", "start": "U1.8", "end": "U2.8", "start_mm": [108.0, 121.78], "end_mm": [160.78, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 298514} +{"net": "/RS_CTS", "start": "U1.9", "end": "U2.9", "start_mm": [108.0, 124.32], "end_mm": [163.32, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 265272} +{"net": "/RS_RI", "start": "U1.6", "end": "U2.10", "start_mm": [108.0, 116.7], "end_mm": [165.86, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 332506} +{"net": "/RS_VALID", "start": "U1.12", "end": "U2.11", "start_mm": [108.0, 131.94], "end_mm": [168.4, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 348384} +{"net": "/BTN_NEXT", "start": "U1.20", "end": "SW3.1", "start_mm": [108.0, 152.26], "end_mm": [167.0, 168.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 272795} +{"net": "/RS_OFF_N", "start": "U1.15", "end": "U2.12", "start_mm": [108.0, 139.56], "end_mm": [170.94, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 351630} +{"net": "/GND", "start": "U1.44", "end": "U1.43", "start_mm": [133.4, 157.34], "end_mm": [133.4, 154.8], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 52} +{"net": "/GND", "start": "SW2.2", "end": "SW1.2", "start_mm": [155.0, 172.5], "end_mm": [149.5, 172.5], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 111} +{"net": "/GND", "start": "SW2.2", "end": "SW3.2", "start_mm": [161.5, 172.5], "end_mm": [167.0, 172.5], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 111} +{"net": "/GND", "start": "SW2.2", "end": "SW2.2", "start_mm": [155.0, 172.5], "end_mm": [161.5, 172.5], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 131} +{"net": "/GND", "start": "SW3.2", "end": "SW3.2", "start_mm": [167.0, 172.5], "end_mm": [173.5, 172.5], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 131} +{"net": "/GND", "start": "SW1.2", "end": "SW1.2", "start_mm": [149.5, 172.5], "end_mm": [143.0, 172.5], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 131} +{"net": "/GND", "start": "DS1.1", "end": "U2.2", "start_mm": [152.19, 137.5], "end_mm": [145.54, 130.0], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 17468} +{"net": "/GND", "start": "SW1.2", "end": "U1.44", "start_mm": [143.0, 172.5], "end_mm": [133.4, 157.34], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 27488} +{"net": "/GND", "start": "U1.44", "end": "U1.22", "start_mm": [133.4, 157.34], "end_mm": [108.0, 157.34], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 73753} +{"net": "/GND", "start": "U1.43", "end": "DS1.1", "start_mm": [133.4, 154.8], "end_mm": [152.19, 137.5], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 54021} +{"net": "/GND", "start": "U2.2", "end": "U1.23", "start_mm": [145.54, 130.0], "end_mm": [133.4, 104.0], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 98250} +{ + "draft_only": true, + "saved": false, + "grid_mm": 0.05, + "clearance_mm": 0.25, + "safety_margin_mm": 0.02, + "via_diameter_mm": 0.7, + "via_drill_mm": 0.3, + "elapsed_seconds": 27.992941715005145, + "routed_tree_edges": 38, + "total_tree_edges": 38, + "tracks": 569, + "vias": 20, + "immutable_identity_sha256": "81def52e6c1d574b4d3ab1a5859a5266b893df0ea6c5b9aa7d7b688cc4a98519", + "input_sha256": "bf94b6c9b00c43a97f933054758a2c9d6541981ae09f2f285dcdb567bd73d9b1", + "validation": "KiCad DRC must be run separately; tree-edge counts are not DRC connectivity" +} diff --git a/hardware/PCB/validation/pcb-routing-input.kicad_pcb b/hardware/PCB/validation/pcb-routing-input.kicad_pcb new file mode 100644 index 0000000..9db8844 --- /dev/null +++ b/hardware/PCB/validation/pcb-routing-input.kicad_pcb @@ -0,0 +1,3022 @@ +(kicad_pcb + (version 20260206) + (generator "pcbnew") + (generator_version "10.0") + (general + (thickness 1.6) + (legacy_teardrops no) + ) + (paper "A4") + (title_block + (title "Serial Swiss Army Knife - 82x80 mm carrier draft") + (rev "A0 DRAFT") + (comment 1 "NOT FOR FABRICATION - male module / USB / antenna geometry unverified") + ) + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user 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"e42ffe5c-7aa5-4770-8cfb-0e94ee336881") + (effects + (font + (size 0.9 0.9) + (thickness 0.15) + ) + ) + ) + (gr_text "NEXT" + (at 170.25 175 0) + (layer "F.SilkS") + (uuid "386e2ef9-9cf9-455d-933f-67c41ac75aea") + (effects + (font + (size 0.9 0.9) + (thickness 0.15) + ) + ) + ) + (gr_text "ESP32 HW678" + (at 120.7 129 0) + (layer "F.SilkS") + (uuid "f45876c7-f270-4231-bfa4-b69ded09f3a4") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (gr_text "26mm OLED" + (at 156 152 0) + (layer "F.SilkS") + (uuid "915becba-730c-42f7-8457-618fb5610a07") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (gr_text "MAX3243 REF" + (at 156.97 121 0) + (layer "F.SilkS") + (uuid "fa700fde-d4f3-437c-9b51-4322d0fd68e0") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (gr_text "Carrier envelope only; module overhang and connector clearance not qualified" + (at 141 97.5 0) + (layer "Dwgs.User") + (uuid "de46e0e9-8a3a-42d0-b1c7-8915a9856836") + (effects + (font + (size 0.9 0.9) + (thickness 0.15) + ) + ) + ) + (gr_text "USB ACCESS - VERIFY" + (at 118 164 0) + (layer "Dwgs.User") + (uuid "c695eb94-004e-4a56-801a-0ca6797a46b2") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (gr_text "VERIFY ANTENNA" + (at 120.5 110 0) + (layer "Dwgs.User") + (uuid "ce061da3-831a-4fb1-9676-9177435d649e") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (gr_text "DE-9 OUT / VERIFY MALE" + (at 156.97 101.5 0) + (layer "Dwgs.User") + (uuid "94303a67-2a65-4a16-9499-2b409a657ba6") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (gr_text "RF RESERVE" + (at 120.5 107 0) + (layer "Dwgs.User") + (uuid "e8228b54-6114-48a6-80ef-7f0a68175b1d") + (effects + (font + (size 1.2 1.2) + (thickness 0.15) + ) + ) + ) + (gr_text "82 x 80 mm / 2 copper layers" + (at 141 95 0) + (layer "Dwgs.User") + (uuid "a742de35-8412-472f-a2e3-0b85d84866bc") + (effects + (font + (size 1.5 1.5) + (thickness 0.15) + ) + ) + ) + (zone + (layers "F.Cu" "B.Cu") + (uuid "4c476672-82f3-4c68-b164-f63aa123584a") + (name "PROVISIONAL RF RESERVE - verify actual antenna clearance") + (hatch edge 0.5) + (connect_pads + (clearance 0) + ) + (min_thickness 0.25) + (keepout + (tracks not_allowed) + (vias not_allowed) + (pads not_allowed) + (copperpour not_allowed) + (footprints allowed) + ) + (placement + (enabled no) + (sheetname "") + ) + (fill + (thermal_gap 0.5) + (thermal_bridge_width 0.5) + (island_removal_mode 0) + ) + (polygon + (pts + (xy 110 100) (xy 131 100) (xy 131 113) (xy 110 113) + ) + ) + ) + (embedded_fonts no) +) diff --git a/hardware/PCB/validation/pcb-routing-pass1-drc.json b/hardware/PCB/validation/pcb-routing-pass1-drc.json new file mode 100644 index 0000000..146dd7c --- /dev/null +++ b/hardware/PCB/validation/pcb-routing-pass1-drc.json @@ -0,0 +1,244 @@ +{ + "$schema": "https://schemas.kicad.org/drc.v1.json", + "coordinate_units": "mm", + "date": "2026-09-20T22:43:07", + "ignored_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "included_severities": [ + "error", + "warning" + ], + "kicad_version": "10.0.6", + "schematic_parity": [], + "source": "serial-carrier.kicad_pcb", + "unconnected_items": [ + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 5 [/RS_DSR] von U1", + "pos": { + "x": 108.0, + "y": 114.16 + }, + "uuid": "0ceca603-53a8-4a53-85cc-f7f8e7be90e4" + }, + { + "description": "Durchsteckpad 7 [/RS_DSR] von U2", + "pos": { + "x": 158.24, + "y": 130.0 + }, + "uuid": "e2d6b2cb-6025-490c-8371-d7cc34ac37f6" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 6 [/RS_RI] von U1", + "pos": { + "x": 108.0, + "y": 116.7 + }, + "uuid": "f35f1696-b778-437b-8cce-67b8c4d5f5d0" + }, + { + "description": "Durchsteckpad 10 [/RS_RI] von U2", + "pos": { + "x": 165.86, + "y": 130.0 + }, + "uuid": "e28de6f2-fb85-4849-ba1a-e98e2a231492" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 7 [/RS_DTR] von U1", + "pos": { + "x": 108.0, + "y": 119.24 + }, + "uuid": "354ab122-85b1-4c9c-9385-d5091fe12303" + }, + { + "description": "Durchsteckpad 6 [/RS_DTR] von U2", + "pos": { + "x": 155.7, + "y": 130.0 + }, + "uuid": "81e8ad67-4bdc-4f57-90b1-68cff6a95261" + } + ], + "severity": "error", + "type": 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+ "y": 114.16 + }, + "uuid": "0ceca603-53a8-4a53-85cc-f7f8e7be90e4" + }, + { + "description": "Durchsteckpad 7 [/RS_DSR] von U2", + "pos": { + "x": 158.24, + "y": 130.0 + }, + "uuid": "e2d6b2cb-6025-490c-8371-d7cc34ac37f6" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 6 [/RS_RI] von U1", + "pos": { + "x": 108.0, + "y": 116.7 + }, + "uuid": "f35f1696-b778-437b-8cce-67b8c4d5f5d0" + }, + { + "description": "Durchsteckpad 10 [/RS_RI] von U2", + "pos": { + "x": 165.86, + "y": 130.0 + }, + "uuid": "e28de6f2-fb85-4849-ba1a-e98e2a231492" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 8 [/RS_RTS] von U1", + "pos": { + "x": 108.0, + "y": 121.78 + }, + "uuid": "55162730-46fd-465d-a1c5-20aed09ed534" + }, + { + "description": "Durchsteckpad 8 [/RS_RTS] von U2", + "pos": { + "x": 160.78, + "y": 130.0 + }, + "uuid": "5c304724-2bc6-409d-9c59-2e40adc557b9" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 9 [/RS_CTS] von U1", + "pos": { + "x": 108.0, + "y": 124.32 + }, + "uuid": "f75c20f8-d3b5-4c3b-9919-cb044b2da5c3" + }, + { + "description": "Durchsteckpad 9 [/RS_CTS] von U2", + "pos": { + "x": 163.32, + "y": 130.0 + }, + "uuid": "a8411036-6859-4041-84b8-2c80c326c58e" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 12 [/RS_VALID] von U1", + "pos": { + "x": 108.0, + "y": 131.94 + }, + "uuid": "2fbc596b-c88f-4fc6-aa94-5dad4fcac9cc" + }, + { + "description": "Durchsteckpad 11 [/RS_VALID] von U2", + "pos": { + "x": 168.4, + "y": 130.0 + }, + "uuid": "9ad42f44-160f-4aa5-bcf0-a4466c090438" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 15 [/RS_OFF_N] von U1", + "pos": { + "x": 108.0, + "y": 139.56 + }, + "uuid": "34e1afe9-b3fc-4d3a-9e33-38b32244f19e" + }, + { + "description": "Durchsteckpad 12 [/RS_OFF_N] von U2", + "pos": { + "x": 170.94, + "y": 130.0 + }, + "uuid": "a43ba2f2-477d-4850-87de-e1591119d5ae" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 17 [/OLED_SDA] von U1", + "pos": { + "x": 108.0, + "y": 144.64 + }, + "uuid": "1f91549c-5cb2-465f-86df-b2f1b0c16ed8" + }, + { + "description": "Durchsteckpad 4 [/OLED_SDA] von DS1", + "pos": { + "x": 159.81, + "y": 137.5 + }, + "uuid": "91a4dcef-1b36-4e3d-a15c-c4578077c27b" + } + ], + "severity": "error", + "type": "unconnected_items" + }, + { + "description": "Missing connection between items", + "items": [ + { + "description": "Durchsteckpad 20 [/BTN_NEXT] von U1", + "pos": { + "x": 108.0, + "y": 152.26 + }, + "uuid": "e7159c90-4e8d-4b21-8e84-a7f59f793440" + }, + { + "description": "Leiterbahn [/BTN_NEXT] auf F.Cu, Länge 6,5000 mm", + "pos": { + "x": 167.0, + "y": 168.0 + }, + "uuid": "97cfdf4d-f068-4e4a-8684-aae638a809ad" + } + ], + "severity": "error", + "type": "unconnected_items" + } + ], + "violations": [] +} diff --git a/hardware/PCB/validation/pcb-routing-pass2.log b/hardware/PCB/validation/pcb-routing-pass2.log new file mode 100644 index 0000000..bbec40b --- /dev/null +++ b/hardware/PCB/validation/pcb-routing-pass2.log @@ -0,0 +1,70 @@ +/builddir/build/BUILD/kicad-10.0.6-build/kicad-10.0.6/include/properties/property.h(607): assert "m_choices.GetCount() > 0" failed in PROPERTY_ENUM(): No enum choices defined +/builddir/build/BUILD/kicad-10.0.6-build/kicad-10.0.6/include/properties/property.h(607): assert "m_choices.GetCount() > 0" failed in PROPERTY_ENUM(): No enum choices defined +/builddir/build/BUILD/kicad-10.0.6-build/kicad-10.0.6/include/properties/property.h(607): assert "m_choices.GetCount() > 0" failed in PROPERTY_ENUM(): No enum choices defined +{"net": "/+3V3", "start": "U1.1", "end": "U1.2", "start_mm": [108.0, 104.0], "end_mm": [108.0, 106.54], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 26} +{"net": "/+3V3", "start": "R2.1", "end": "DS1.2", "start_mm": [154.0, 134.0], "end_mm": [154.73, 137.5], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 239} +{"net": "/+3V3", "start": "U2.1", "end": "R1.1", "start_mm": [143.0, 130.0], "end_mm": [143.0, 134.0], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 41} +{"net": "/BTN_NEXT", "start": "SW3.1", "end": "SW3.1", "start_mm": [167.0, 168.0], "end_mm": [173.5, 168.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 66} +{"net": "/BTN_PREVIOUS", "start": "SW1.1", "end": "SW1.1", "start_mm": [149.5, 168.0], "end_mm": [143.0, 168.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 66} +{"net": "/BTN_SELECT", "start": "SW2.1", "end": "SW2.1", "start_mm": [155.0, 168.0], "end_mm": [161.5, 168.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 66} +{"net": "/+3V3", "start": "DS1.2", "end": "R3.1", "start_mm": [154.73, 137.5], "end_mm": [165.0, 134.0], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 1334} +{"net": "/+3V3", "start": "R1.1", "end": "R2.1", "start_mm": [143.0, 134.0], "end_mm": [154.0, 134.0], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 3711} +{"net": "/BTN_SELECT", "start": "SW2.1", "end": "R2.2", "start_mm": [161.5, 168.0], "end_mm": [161.62, 134.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 681} +{"net": "/BTN_NEXT", "start": "SW3.1", "end": "R3.2", "start_mm": [173.5, 168.0], "end_mm": [172.62, 134.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 3329} +{"net": "/BTN_PREVIOUS", "start": "R1.2", "end": "SW1.1", "start_mm": [150.62, 134.0], "end_mm": [149.5, 168.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 3971} +{"net": "/+3V3", "start": "U1.2", "end": "U2.1", "start_mm": [108.0, 106.54], "end_mm": [143.0, 130.0], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 224476} +{"net": "/RS_RX", "start": "U1.11", "end": "U2.4", "start_mm": [108.0, 129.4], "end_mm": [150.62, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 274662} +{"net": "/BTN_PREVIOUS", "start": "U1.16", "end": "R1.2", "start_mm": [108.0, 142.1], "end_mm": [150.62, 134.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 227867} +{"net": "/RS_DCD", "start": "U1.4", "end": "U2.3", "start_mm": [108.0, 111.62], "end_mm": [148.08, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 201896} +{"net": "/RS_TX", "start": "U1.10", "end": "U2.5", "start_mm": [108.0, 126.86], "end_mm": [153.16, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 271117} +{"net": "/RS_DTR", "start": "U1.7", "end": "U2.6", "start_mm": [108.0, 119.24], "end_mm": [155.7, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 307013} +{"net": "/OLED_SCL", "start": "U1.18", "end": "DS1.3", "start_mm": [108.0, 147.18], "end_mm": [157.27, 137.5], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 127246} +{"net": "/BTN_SELECT", "start": "SW2.1", "end": "U1.19", "start_mm": [155.0, 168.0], "end_mm": [108.0, 149.72], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 73189} +{"net": "/OLED_SDA", "start": "U1.17", "end": "DS1.4", "start_mm": [108.0, 144.64], "end_mm": [159.81, 137.5], "routed": false, "width_mm": 0.25, "power_fallback": false, "expansions": 272010} +{"net": "/RS_DSR", "start": "U1.5", "end": "U2.7", "start_mm": [108.0, 114.16], "end_mm": [158.24, 130.0], "routed": false, "width_mm": 0.25, "power_fallback": false, "expansions": 272046} +{"net": "/RS_RTS", "start": "U1.8", "end": "U2.8", "start_mm": [108.0, 121.78], "end_mm": [160.78, 130.0], "routed": false, "width_mm": 0.25, "power_fallback": false, "expansions": 272010} +{"net": "/RS_CTS", "start": "U1.9", "end": "U2.9", "start_mm": [108.0, 124.32], "end_mm": [163.32, 130.0], "routed": false, "width_mm": 0.25, "power_fallback": false, "expansions": 272000} +{"net": "/RS_RI", "start": "U1.6", "end": "U2.10", "start_mm": [108.0, 116.7], "end_mm": [165.86, 130.0], "routed": false, "width_mm": 0.25, "power_fallback": false, "expansions": 272008} +{"net": "/RS_VALID", "start": "U1.12", "end": "U2.11", "start_mm": [108.0, 131.94], "end_mm": [168.4, 130.0], "routed": false, "width_mm": 0.25, "power_fallback": false, "expansions": 272015} +{"net": "/BTN_NEXT", "start": "U1.20", "end": "SW3.1", "start_mm": [108.0, 152.26], "end_mm": [167.0, 168.0], "routed": false, "width_mm": 0.25, "power_fallback": false, "expansions": 272010} +{"net": "/RS_OFF_N", "start": "U1.15", "end": "U2.12", "start_mm": [108.0, 139.56], "end_mm": [170.94, 130.0], "routed": false, "width_mm": 0.25, "power_fallback": false, "expansions": 272010} +{"net": "/GND", "start": "U1.44", "end": "U1.43", "start_mm": [133.4, 157.34], "end_mm": [133.4, 154.8], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 26} +{"net": "/GND", "start": "SW2.2", "end": "SW1.2", "start_mm": [155.0, 172.5], "end_mm": [149.5, 172.5], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 56} +{"net": "/GND", "start": "SW2.2", "end": "SW3.2", "start_mm": [161.5, 172.5], "end_mm": [167.0, 172.5], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 56} +{"net": "/GND", "start": "SW2.2", "end": "SW2.2", "start_mm": [155.0, 172.5], "end_mm": [161.5, 172.5], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 66} +{"net": "/GND", "start": "SW3.2", "end": "SW3.2", "start_mm": [167.0, 172.5], "end_mm": [173.5, 172.5], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 66} +{"net": "/GND", "start": "SW1.2", "end": "SW1.2", "start_mm": [149.5, 172.5], "end_mm": [143.0, 172.5], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 66} +{"net": "/GND", "start": "DS1.1", "end": "U2.2", "start_mm": [152.19, 137.5], "end_mm": [145.54, 130.0], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 3234} +{"net": "/GND", "start": "SW1.2", "end": "U1.44", "start_mm": [143.0, 172.5], "end_mm": [133.4, 157.34], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 29110} +{"net": "/GND", "start": "U1.44", "end": "U1.22", "start_mm": [133.4, 157.34], "end_mm": [108.0, 157.34], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 16915} +{"net": "/GND", "start": "U1.43", "end": "DS1.1", "start_mm": [133.4, 154.8], "end_mm": [152.19, 137.5], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 57470} +{"net": "/GND", "start": "U2.2", "end": "U1.23", "start_mm": [145.54, 130.0], "end_mm": [133.4, 104.0], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 34158} +22:45:50: Debug: Adding duplicate image handler for 'PNG file' +22:45:50: Debug: Adding duplicate image handler for 'JPEG file' +22:45:50: Debug: Adding duplicate image handler for 'TIFF file' +22:45:50: Debug: Adding duplicate image handler for 'GIF file' +22:45:50: Debug: Adding duplicate image handler for 'PNM file' +22:45:50: Debug: Adding duplicate image handler for 'PCX file' +22:45:50: Debug: Adding duplicate image handler for 'IFF file' +22:45:50: Debug: Adding duplicate image handler for 'Windows icon file' +22:45:50: Debug: Adding duplicate image handler for 'Windows cursor file' +22:45:50: Debug: Adding duplicate image handler for 'Windows animated cursor file' +22:45:50: Debug: Adding duplicate image handler for 'TGA file' +22:45:50: Debug: Adding duplicate image handler for 'XPM file' +{ + "draft_only": true, + "saved": true, + "grid_mm": 0.1, + "clearance_mm": 0.25, + "safety_margin_mm": 0.04, + "via_diameter_mm": 0.7, + "via_drill_mm": 0.3, + "elapsed_seconds": 20.799824999005068, + "routed_tree_edges": 30, + "total_tree_edges": 38, + "tracks": 248, + "vias": 13, + "immutable_identity_sha256": "81def52e6c1d574b4d3ab1a5859a5266b893df0ea6c5b9aa7d7b688cc4a98519", + "input_sha256": "ab3f0775dee575a11d06f80996169f5097dfff672b69152ad9b559707f70009b", + "validation": "KiCad DRC must be run separately; tree-edge counts are not DRC connectivity" +} diff --git a/hardware/PCB/validation/pcb-routing-pass3.log b/hardware/PCB/validation/pcb-routing-pass3.log new file mode 100644 index 0000000..0be6007 --- /dev/null +++ b/hardware/PCB/validation/pcb-routing-pass3.log @@ -0,0 +1,70 @@ +/builddir/build/BUILD/kicad-10.0.6-build/kicad-10.0.6/include/properties/property.h(607): assert "m_choices.GetCount() > 0" failed in PROPERTY_ENUM(): No enum choices defined +/builddir/build/BUILD/kicad-10.0.6-build/kicad-10.0.6/include/properties/property.h(607): assert "m_choices.GetCount() > 0" failed in PROPERTY_ENUM(): No enum choices defined +/builddir/build/BUILD/kicad-10.0.6-build/kicad-10.0.6/include/properties/property.h(607): assert "m_choices.GetCount() > 0" failed in PROPERTY_ENUM(): No enum choices defined +{"net": "/+3V3", "start": "U1.1", "end": "U1.2", "start_mm": [108.0, 104.0], "end_mm": [108.0, 106.54], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 52} +{"net": "/+3V3", "start": "R2.1", "end": "DS1.2", "start_mm": [154.0, 134.0], "end_mm": [154.73, 137.5], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 911} +{"net": "/+3V3", "start": "U2.1", "end": "R1.1", "start_mm": [143.0, 130.0], "end_mm": [143.0, 134.0], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 81} +{"net": "/BTN_NEXT", "start": "SW3.1", "end": "SW3.1", "start_mm": [167.0, 168.0], "end_mm": [173.5, 168.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 131} +{"net": "/BTN_PREVIOUS", "start": "SW1.1", "end": "SW1.1", "start_mm": [149.5, 168.0], "end_mm": [143.0, 168.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 131} +{"net": "/BTN_SELECT", "start": "SW2.1", "end": "SW2.1", "start_mm": [155.0, 168.0], "end_mm": [161.5, 168.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 131} +{"net": "/+3V3", "start": "DS1.2", "end": "R3.1", "start_mm": [154.73, 137.5], "end_mm": [165.0, 134.0], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 5139} +{"net": "/+3V3", "start": "R1.1", "end": "R2.1", "start_mm": [143.0, 134.0], "end_mm": [154.0, 134.0], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 14153} +{"net": "/BTN_SELECT", "start": "SW2.1", "end": "R2.2", "start_mm": [161.5, 168.0], "end_mm": [161.62, 134.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 2039} +{"net": "/BTN_NEXT", "start": "SW3.1", "end": "R3.2", "start_mm": [173.5, 168.0], "end_mm": [172.62, 134.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 12615} +{"net": "/BTN_PREVIOUS", "start": "R1.2", "end": "SW1.1", "start_mm": [150.62, 134.0], "end_mm": [149.5, 168.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 15179} +{"net": "/+3V3", "start": "U1.2", "end": "U2.1", "start_mm": [108.0, 106.54], "end_mm": [143.0, 130.0], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 894511} +{"net": "/RS_RX", "start": "U1.11", "end": "U2.4", "start_mm": [108.0, 129.4], "end_mm": [150.62, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 51516} +{"net": "/BTN_PREVIOUS", "start": "U1.16", "end": "R1.2", "start_mm": [108.0, 142.1], "end_mm": [150.62, 134.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 94479} +{"net": "/RS_DCD", "start": "U1.4", "end": "U2.3", "start_mm": [108.0, 111.62], "end_mm": [148.08, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 266031} +{"net": "/RS_TX", "start": "U1.10", "end": "U2.5", "start_mm": [108.0, 126.86], "end_mm": [153.16, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 175689} +{"net": "/RS_DTR", "start": "U1.7", "end": "U2.6", "start_mm": [108.0, 119.24], "end_mm": [155.7, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 326823} +{"net": "/OLED_SCL", "start": "U1.18", "end": "DS1.3", "start_mm": [108.0, 147.18], "end_mm": [157.27, 137.5], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 82557} +{"net": "/BTN_SELECT", "start": "SW2.1", "end": "U1.19", "start_mm": [155.0, 168.0], "end_mm": [108.0, 149.72], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 147997} +{"net": "/OLED_SDA", "start": "U1.17", "end": "DS1.4", "start_mm": [108.0, 144.64], "end_mm": [159.81, 137.5], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 266428} +{"net": "/RS_DSR", "start": "U1.5", "end": "U2.7", "start_mm": [108.0, 114.16], "end_mm": [158.24, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 372014} +{"net": "/RS_RTS", "start": "U1.8", "end": "U2.8", "start_mm": [108.0, 121.78], "end_mm": [160.78, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 298514} +{"net": "/RS_CTS", "start": "U1.9", "end": "U2.9", "start_mm": [108.0, 124.32], "end_mm": [163.32, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 265272} +{"net": "/RS_RI", "start": "U1.6", "end": "U2.10", "start_mm": [108.0, 116.7], "end_mm": [165.86, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 332506} +{"net": "/RS_VALID", "start": "U1.12", "end": "U2.11", "start_mm": [108.0, 131.94], "end_mm": [168.4, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 348384} +{"net": "/BTN_NEXT", "start": "U1.20", "end": "SW3.1", "start_mm": [108.0, 152.26], "end_mm": [167.0, 168.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 272795} +{"net": "/RS_OFF_N", "start": "U1.15", "end": "U2.12", "start_mm": [108.0, 139.56], "end_mm": [170.94, 130.0], "routed": true, "width_mm": 0.25, "power_fallback": false, "expansions": 351630} +{"net": "/GND", "start": "U1.44", "end": "U1.43", "start_mm": [133.4, 157.34], "end_mm": [133.4, 154.8], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 52} +{"net": "/GND", "start": "SW2.2", "end": "SW1.2", "start_mm": [155.0, 172.5], "end_mm": [149.5, 172.5], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 111} +{"net": "/GND", "start": "SW2.2", "end": "SW3.2", "start_mm": [161.5, 172.5], "end_mm": [167.0, 172.5], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 111} +{"net": "/GND", "start": "SW2.2", "end": "SW2.2", "start_mm": [155.0, 172.5], "end_mm": [161.5, 172.5], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 131} +{"net": "/GND", "start": "SW3.2", "end": "SW3.2", "start_mm": [167.0, 172.5], "end_mm": [173.5, 172.5], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 131} +{"net": "/GND", "start": "SW1.2", "end": "SW1.2", "start_mm": [149.5, 172.5], "end_mm": [143.0, 172.5], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 131} +{"net": "/GND", "start": "DS1.1", "end": "U2.2", "start_mm": [152.19, 137.5], "end_mm": [145.54, 130.0], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 17468} +{"net": "/GND", "start": "SW1.2", "end": "U1.44", "start_mm": [143.0, 172.5], "end_mm": [133.4, 157.34], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 27488} +{"net": "/GND", "start": "U1.44", "end": "U1.22", "start_mm": [133.4, 157.34], "end_mm": [108.0, 157.34], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 73753} +{"net": "/GND", "start": "U1.43", "end": "DS1.1", "start_mm": [133.4, 154.8], "end_mm": [152.19, 137.5], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 54021} +{"net": "/GND", "start": "U2.2", "end": "U1.23", "start_mm": [145.54, 130.0], "end_mm": [133.4, 104.0], "routed": true, "width_mm": 0.5, "power_fallback": false, "expansions": 98250} +22:47:09: Debug: Adding duplicate image handler for 'PNG file' +22:47:09: Debug: Adding duplicate image handler for 'JPEG file' +22:47:09: Debug: Adding duplicate image handler for 'TIFF file' +22:47:09: Debug: Adding duplicate image handler for 'GIF file' +22:47:09: Debug: Adding duplicate image handler for 'PNM file' +22:47:09: Debug: Adding duplicate image handler for 'PCX file' +22:47:09: Debug: Adding duplicate image handler for 'IFF file' +22:47:09: Debug: Adding duplicate image handler for 'Windows icon file' +22:47:09: Debug: Adding duplicate image handler for 'Windows cursor file' +22:47:09: Debug: Adding duplicate image handler for 'Windows animated cursor file' +22:47:09: Debug: Adding duplicate image handler for 'TGA file' +22:47:09: Debug: Adding duplicate image handler for 'XPM file' +{ + "draft_only": true, + "saved": true, + "grid_mm": 0.05, + "clearance_mm": 0.25, + "safety_margin_mm": 0.02, + "via_diameter_mm": 0.7, + "via_drill_mm": 0.3, + "elapsed_seconds": 26.517815405000874, + "routed_tree_edges": 38, + "total_tree_edges": 38, + "tracks": 569, + "vias": 20, + "immutable_identity_sha256": "81def52e6c1d574b4d3ab1a5859a5266b893df0ea6c5b9aa7d7b688cc4a98519", + "input_sha256": "41643d6089dae5ef2eee1a2071a6d11ae4c00f3c922eddfeaafff619fc5fab19", + "validation": "KiCad DRC must be run separately; tree-edge counts are not DRC connectivity" +} diff --git a/hardware/PCB/validation/pcb-routing-run.json b/hardware/PCB/validation/pcb-routing-run.json new file mode 100644 index 0000000..70611b4 --- /dev/null +++ b/hardware/PCB/validation/pcb-routing-run.json @@ -0,0 +1,665 @@ +{ + "draft_only": true, + "saved": true, + "grid_mm": 0.05, + "clearance_mm": 0.25, + "safety_margin_mm": 0.02, + "via_diameter_mm": 0.7, + "via_drill_mm": 0.3, + "elapsed_seconds": 26.517815405000874, + "connections": [ + { + "net": "/+3V3", + "start": "U1.1", + "end": "U1.2", + "start_mm": [ + 108.0, + 104.0 + ], + "end_mm": [ + 108.0, + 106.54 + ], + "routed": true, + "width_mm": 0.5, + "power_fallback": false, + "expansions": 52 + }, + { + "net": "/+3V3", + "start": "R2.1", + "end": "DS1.2", + "start_mm": [ + 154.0, + 134.0 + ], + "end_mm": [ + 154.73, + 137.5 + ], + "routed": true, + "width_mm": 0.5, + "power_fallback": false, + "expansions": 911 + }, + { + "net": "/+3V3", + "start": "U2.1", + "end": "R1.1", + "start_mm": [ + 143.0, + 130.0 + ], + "end_mm": [ + 143.0, + 134.0 + ], + "routed": true, + "width_mm": 0.5, + "power_fallback": false, + "expansions": 81 + }, + { + "net": "/BTN_NEXT", + "start": "SW3.1", + "end": "SW3.1", + "start_mm": [ + 167.0, + 168.0 + ], + "end_mm": [ + 173.5, + 168.0 + ], + "routed": true, + "width_mm": 0.25, + "power_fallback": false, + "expansions": 131 + }, + { + "net": "/BTN_PREVIOUS", + "start": "SW1.1", + "end": "SW1.1", + "start_mm": [ + 149.5, + 168.0 + ], + "end_mm": [ + 143.0, + 168.0 + ], + "routed": true, + "width_mm": 0.25, + "power_fallback": false, + "expansions": 131 + }, + { + "net": "/BTN_SELECT", + "start": "SW2.1", + "end": "SW2.1", + "start_mm": [ + 155.0, + 168.0 + ], + "end_mm": [ + 161.5, + 168.0 + ], + "routed": true, + "width_mm": 0.25, + "power_fallback": false, + "expansions": 131 + }, + { + "net": "/+3V3", + "start": "DS1.2", + "end": "R3.1", + "start_mm": [ + 154.73, + 137.5 + ], + "end_mm": [ + 165.0, + 134.0 + ], + "routed": true, + "width_mm": 0.5, + "power_fallback": false, + "expansions": 5139 + }, + { + "net": "/+3V3", + "start": "R1.1", + "end": "R2.1", + "start_mm": [ + 143.0, + 134.0 + ], + "end_mm": [ + 154.0, + 134.0 + ], + "routed": true, + "width_mm": 0.5, + "power_fallback": false, + "expansions": 14153 + }, + { + "net": "/BTN_SELECT", + "start": "SW2.1", + "end": "R2.2", + "start_mm": [ + 161.5, + 168.0 + ], + "end_mm": [ + 161.62, + 134.0 + ], + "routed": true, + "width_mm": 0.25, + "power_fallback": false, + "expansions": 2039 + }, + { + "net": "/BTN_NEXT", + "start": "SW3.1", + "end": "R3.2", + "start_mm": [ + 173.5, + 168.0 + ], + "end_mm": [ + 172.62, + 134.0 + ], + "routed": true, + "width_mm": 0.25, + "power_fallback": false, + "expansions": 12615 + }, + { + "net": "/BTN_PREVIOUS", + "start": "R1.2", + "end": "SW1.1", + "start_mm": [ + 150.62, + 134.0 + ], + "end_mm": [ + 149.5, + 168.0 + ], + "routed": true, + "width_mm": 0.25, + "power_fallback": false, + "expansions": 15179 + }, + { + "net": "/+3V3", + "start": "U1.2", + "end": "U2.1", + "start_mm": [ + 108.0, + 106.54 + ], + "end_mm": [ + 143.0, + 130.0 + ], + "routed": true, + "width_mm": 0.5, + "power_fallback": false, + "expansions": 894511 + }, + { + "net": "/RS_RX", + "start": "U1.11", + "end": "U2.4", + "start_mm": [ + 108.0, + 129.4 + ], + "end_mm": [ + 150.62, + 130.0 + ], + "routed": true, + "width_mm": 0.25, + "power_fallback": false, + "expansions": 51516 + }, + { + "net": "/BTN_PREVIOUS", + "start": "U1.16", + "end": "R1.2", + "start_mm": [ + 108.0, + 142.1 + ], + "end_mm": [ + 150.62, + 134.0 + ], + "routed": true, + "width_mm": 0.25, + "power_fallback": false, + "expansions": 94479 + }, + { + "net": "/RS_DCD", + "start": "U1.4", + "end": "U2.3", + "start_mm": [ + 108.0, + 111.62 + ], + "end_mm": [ + 148.08, + 130.0 + ], + "routed": true, + "width_mm": 0.25, + "power_fallback": false, + "expansions": 266031 + }, + { + "net": "/RS_TX", + "start": "U1.10", + "end": "U2.5", + "start_mm": [ + 108.0, + 126.86 + ], + "end_mm": [ + 153.16, + 130.0 + ], + "routed": true, + "width_mm": 0.25, + "power_fallback": false, + "expansions": 175689 + }, + { + "net": "/RS_DTR", + "start": "U1.7", + "end": "U2.6", + "start_mm": [ + 108.0, + 119.24 + ], + "end_mm": [ + 155.7, + 130.0 + ], + "routed": true, + "width_mm": 0.25, + "power_fallback": false, + "expansions": 326823 + }, + { + "net": "/OLED_SCL", + "start": "U1.18", + "end": "DS1.3", + "start_mm": [ + 108.0, + 147.18 + ], + "end_mm": [ + 157.27, + 137.5 + ], + "routed": true, + "width_mm": 0.25, + "power_fallback": false, + "expansions": 82557 + }, + { + "net": "/BTN_SELECT", + "start": "SW2.1", + "end": "U1.19", + "start_mm": [ + 155.0, + 168.0 + ], + "end_mm": [ + 108.0, + 149.72 + ], + "routed": true, + "width_mm": 0.25, + "power_fallback": false, + "expansions": 147997 + }, + { + "net": "/OLED_SDA", + "start": "U1.17", + "end": "DS1.4", + "start_mm": [ + 108.0, + 144.64 + ], + "end_mm": [ + 159.81, + 137.5 + ], + "routed": true, + "width_mm": 0.25, + "power_fallback": false, + "expansions": 266428 + }, + { + "net": "/RS_DSR", + "start": "U1.5", + "end": "U2.7", + "start_mm": [ + 108.0, + 114.16 + ], + "end_mm": [ + 158.24, + 130.0 + ], + "routed": true, + "width_mm": 0.25, + "power_fallback": false, + "expansions": 372014 + }, + { + "net": "/RS_RTS", + "start": "U1.8", + "end": "U2.8", + "start_mm": [ + 108.0, + 121.78 + ], + "end_mm": [ + 160.78, + 130.0 + ], + "routed": true, + "width_mm": 0.25, + "power_fallback": false, + "expansions": 298514 + }, + { + "net": "/RS_CTS", + "start": "U1.9", + "end": "U2.9", + "start_mm": [ + 108.0, + 124.32 + ], + "end_mm": [ + 163.32, + 130.0 + ], + "routed": true, + "width_mm": 0.25, + "power_fallback": false, + "expansions": 265272 + }, + { + "net": "/RS_RI", + "start": "U1.6", + "end": "U2.10", + "start_mm": [ + 108.0, + 116.7 + ], + "end_mm": [ + 165.86, + 130.0 + ], + "routed": true, + "width_mm": 0.25, + "power_fallback": false, + "expansions": 332506 + }, + { + "net": "/RS_VALID", + "start": "U1.12", + "end": "U2.11", + "start_mm": [ + 108.0, + 131.94 + ], + "end_mm": [ + 168.4, + 130.0 + ], + "routed": true, + "width_mm": 0.25, + "power_fallback": false, + "expansions": 348384 + }, + { + "net": "/BTN_NEXT", + "start": "U1.20", + "end": "SW3.1", + "start_mm": [ + 108.0, + 152.26 + ], + "end_mm": [ + 167.0, + 168.0 + ], + "routed": true, + "width_mm": 0.25, + "power_fallback": false, + "expansions": 272795 + }, + { + "net": "/RS_OFF_N", + "start": "U1.15", + "end": "U2.12", + "start_mm": [ + 108.0, + 139.56 + ], + "end_mm": [ + 170.94, + 130.0 + ], + "routed": true, + "width_mm": 0.25, + "power_fallback": false, + "expansions": 351630 + }, + { + "net": "/GND", + "start": "U1.44", + "end": "U1.43", + "start_mm": [ + 133.4, + 157.34 + ], + "end_mm": [ + 133.4, + 154.8 + ], + "routed": true, + "width_mm": 0.5, + "power_fallback": false, + "expansions": 52 + }, + { + "net": "/GND", + "start": "SW2.2", + "end": "SW1.2", + "start_mm": [ + 155.0, + 172.5 + ], + "end_mm": [ + 149.5, + 172.5 + ], + "routed": true, + "width_mm": 0.5, + "power_fallback": false, + "expansions": 111 + }, + { + "net": "/GND", + "start": "SW2.2", + "end": "SW3.2", + "start_mm": [ + 161.5, + 172.5 + ], + "end_mm": [ + 167.0, + 172.5 + ], + "routed": true, + "width_mm": 0.5, + "power_fallback": false, + "expansions": 111 + }, + { + "net": "/GND", + "start": "SW2.2", + "end": "SW2.2", + "start_mm": [ + 155.0, + 172.5 + ], + "end_mm": [ + 161.5, + 172.5 + ], + "routed": true, + "width_mm": 0.5, + "power_fallback": false, + "expansions": 131 + }, + { + "net": "/GND", + "start": "SW3.2", + "end": "SW3.2", + "start_mm": [ + 167.0, + 172.5 + ], + "end_mm": [ + 173.5, + 172.5 + ], + "routed": true, + "width_mm": 0.5, + "power_fallback": false, + "expansions": 131 + }, + { + "net": "/GND", + "start": "SW1.2", + "end": "SW1.2", + "start_mm": [ + 149.5, + 172.5 + ], + "end_mm": [ + 143.0, + 172.5 + ], + "routed": true, + "width_mm": 0.5, + "power_fallback": false, + "expansions": 131 + }, + { + "net": "/GND", + "start": "DS1.1", + "end": "U2.2", + "start_mm": [ + 152.19, + 137.5 + ], + "end_mm": [ + 145.54, + 130.0 + ], + "routed": true, + "width_mm": 0.5, + "power_fallback": false, + "expansions": 17468 + }, + { + "net": "/GND", + "start": "SW1.2", + "end": "U1.44", + "start_mm": [ + 143.0, + 172.5 + ], + "end_mm": [ + 133.4, + 157.34 + ], + "routed": true, + "width_mm": 0.5, + "power_fallback": false, + "expansions": 27488 + }, + { + "net": "/GND", + "start": "U1.44", + "end": "U1.22", + "start_mm": [ + 133.4, + 157.34 + ], + "end_mm": [ + 108.0, + 157.34 + ], + "routed": true, + "width_mm": 0.5, + "power_fallback": false, + "expansions": 73753 + }, + { + "net": "/GND", + "start": "U1.43", + "end": "DS1.1", + "start_mm": [ + 133.4, + 154.8 + ], + "end_mm": [ + 152.19, + 137.5 + ], + "routed": true, + "width_mm": 0.5, + "power_fallback": false, + "expansions": 54021 + }, + { + "net": "/GND", + "start": "U2.2", + "end": "U1.23", + "start_mm": [ + 145.54, + 130.0 + ], + "end_mm": [ + 133.4, + 104.0 + ], + "routed": true, + "width_mm": 0.5, + "power_fallback": false, + "expansions": 98250 + } + ], + "routed_tree_edges": 38, + "total_tree_edges": 38, + "tracks": 569, + "vias": 20, + "immutable_identity_sha256": "81def52e6c1d574b4d3ab1a5859a5266b893df0ea6c5b9aa7d7b688cc4a98519", + "input_sha256": "41643d6089dae5ef2eee1a2071a6d11ae4c00f3c922eddfeaafff619fc5fab19", + "validation": "KiCad DRC must be run separately; tree-edge counts are not DRC connectivity" +} diff --git a/hardware/PCB/validation/pcb-routing-summary.md b/hardware/PCB/validation/pcb-routing-summary.md new file mode 100644 index 0000000..ff0d8af --- /dev/null +++ b/hardware/PCB/validation/pcb-routing-summary.md @@ -0,0 +1,139 @@ +# Two-layer draft routing result + +Date: 2026-09-20. KiCad 10.0.6; system `/usr/bin/python3`. + +## Saved result + +Actual copper routing is saved in `../serial-carrier.kicad_pcb`, not just a preview +or an exported proposal. **38/38 required spanning-tree connections across 17 +multi-pad nets routed; KiCad reports 0 unconnected items, 0 errors, 0 warnings.** +Intentional single-pad `unconnected-(...)` nets retain their original names and +are not connected to anything else. + +- Two copper layers, F.Cu and B.Cu. +- 569 straight track segments: 425 at 0.25 mm for signals and 144 at 0.5 mm for + +3V3/GND. No narrow power-track fallback was necessary. +- 20 through vias, 0.7 mm copper diameter / 0.3 mm drill. +- No copper pours: all ground connections were routed explicitly. +- Original RF rule area, x110..131 / y100..113 mm on both copper layers, preserved. + No tracks, vias or fills enter the reservation. Minimum copper-to-reservation + gap measured independently is 0.025 mm; this is geometric compliance with the + specified provisional boundary, **not validation of an antenna's RF needs**. +- All 9 electrical footprints and 4 standalone mounting footprints preserved. + Pad positions, shapes, sizes, drills, types, nets, functions, pin types and UUIDs; + footprint placement, orientation, library IDs, values, UUIDs and schematic UUID + paths; net table, outline and RF rule-area geometry/flags match the input. +- Generator, README, schematic, project and libraries were not edited by routing. + No external network dependency or manufacturing exports were used. + +## Validation performed + +From `hardware/PCB`: + +```sh +kicad-cli pcb drc --format json --refill-zones --save-board -o validation/pcb-routing-drc.json serial-carrier.kicad_pcb +kicad-cli pcb drc --format json --all-track-errors --severity-all --exit-code-violations -o validation/pcb-routing-all-drc.json serial-carrier.kicad_pcb +/usr/bin/python3 -B validation/pcb-routing-check.py +``` + +Both DRC runs: **0 violations and 0 unconnected items**. No DRC settings or +exclusions were added or changed. Existing project rules specify 0.25 mm minimum +clearance, 0.5 mm copper-edge clearance, 0.25 mm minimum track width and 0.7 mm +minimum via diameter. + +Independent continuous-geometry audit (`pcb-routing-check.json`): + +| Check | Measured minimum | Requirement | +|---|---:|---:| +| Different-net copper / copper-to-NPTH clearance | 0.275 mm | 0.25 mm | +| Copper or NPTH edge to board edge | 0.525 mm | 0.5 mm | +| Copper / NPTH edge to RF reserve | 0.025 mm | No intersection | +| Via drill edge to another drilled hole edge | 0.840175 mm | 0.25 mm | + +The audit uses exact straight-line/point/rectangle distance calculations with +copper radii, rather than the router's raster masks. It also verifies dimensions, +source-preservation invariants, and three overwrite-refusal cases. Requires +locally installed `pcbnew`, NumPy and Shapely; the router itself only needs +`pcbnew` and NumPy. + +DRC still honors the project's pre-existing ignored checks: +`missing_courtyard`, `track_not_centered_on_via`, +`tuning_profile_track_geometries`, `footprint_filters_mismatch`, and +`footprint_type_mismatch`. `--severity-all` does not enable ignored checks. +The routing subtask compared electrical UUID linkage and pad-net assignments +with the input board. Subsequent integration also ran fresh schematic-parity DRC +and added missing symbol metadata fields to the PCB without changing copper. +That check reports exactly one expected U2 footprint warning (provisional PCB +footprint versus intentionally blank schematic assignment); no net mismatch. +See `pcb-parity-drc.json` and `pcb-validation-summary.json`. + +## Method and bounded passes + +`../route_pcb_draft.py` uses a two-layer 8-direction raster A* search, an explicit +via cost, exact-pad-centre terminal stubs, conservative foreign-copper and hole +obstacles, and only collinear path compression. It preserves the L-shaped edge +and RF reservation. Per-net minimum spanning trees connect every physical pad, +including duplicate switch contacts; short links precede longer links and GND is +last. It does not optimize return-current paths, topology or total via count. + +1. Initial 0.1 mm raster / 0.04 mm safety margin / 250,000 expansions per search: + 29/38 connections; DRC 0 violations, 9 unconnected. +2. Increased search allowance to 1,200,000 expansions: 30/38; DRC 0 violations, + 8 unconnected. Some raster header passages were blocked, not just expensive. +3. Final 0.05 mm raster / 0.02 mm additional safety margin, with 0.25 mm physical + clearance unchanged: 38/38 in approximately 26.5 seconds; DRC fully connected. + Each pass had a 240-second routing deadline. No unresolved routing remains. + +A KiCad Python binding ownership problem in the first replacement attempt caused +an exception/segfault before any board save. Replacement now uses `board.Delete` +instead of `board.Remove`; the subsequent save and no-save rerun both passed. +The known startup PROPERTY_ENUM assertions do not prevent validation. + +## Rerun safety + +By default the script never saves. The existing routed board is protected even +from a preview unless `--replace-routes` is given. A preview can be run with: + +```sh +/usr/bin/python3 -B route_pcb_draft.py --replace-routes --seconds 240 +``` + +This exact no-save workflow was tested: it again found 38/38 connections, 569 +segments and 20 vias, and left the board byte-for-byte unchanged. + +**The following command discards all existing/manual tracks and vias**, then +replaces them with fresh draft routing. Back up manual work first: + +```sh +/usr/bin/python3 -B route_pcb_draft.py --route --overwrite --replace-routes --seconds 240 --max-expansions 1200000 +``` + +The script refuses a PCB-editor lock, unexpected outline/RF/board structure, +unsupported pad orientation/layers, unapproved existing routes, or detected board +changes before save. Candidate serialization must preserve immutable geometry +and linkage before replacing the board. It deliberately does not run DRC itself: +rerun the validation commands after any routing change. Runtime/expansion limits +can produce a partial board; inspect both the run report and actual DRC, not just +the script exit status. + +## Evidence and remaining limitations + +- `pcb-routing-input.kicad_pcb`: unrouted input snapshot, after baseline DRC save. +- `pcb-routing-baseline.json`: 38 unconnected / no violations before routing. +- `pcb-routing-pass1-drc.json`, `pcb-routing-pass2-drc.json`: intermediate DRC. +- `pcb-routing-pass2.log`, `pcb-routing-pass3.log`: bounded routing progress. +- `pcb-routing-run.json`: final saved-route metrics and connection list. +- `pcb-routing-drc.json`, `pcb-routing-all-drc.json`: final KiCad DRC evidence. +- `pcb-routing-check.py`, `pcb-routing-check.json`: repeatable independent audit. +- `pcb-routing-dry-run.log`: successful final no-save reproduction. + +Routing-only DRC-saved snapshot SHA-256 (before integration copied schematic +metadata fields): `bf94b6c9b00c43a97f933054758a2c9d6541981ae09f2f285dcdb567bd73d9b1`. +The current post-integration hash is recorded by `pcb-routing-check.json`; +geometry, pad-net linkage and copper are unchanged by the metadata copy. + +**Still DRAFT / NOT FOR FABRICATION.** Provisional module/connector geometry, +antenna envelope, assembly/courtyard clearances, USB access, male RS-232 connector +fit, physical pin mapping, power integrity, EMI and hardware operation are not +qualified by routing or DRC. All previously documented mechanical/electrical +release gates remain. No physical-device or manufacturing validation performed. diff --git a/hardware/PCB/validation/pcb-source-netlist.xml b/hardware/PCB/validation/pcb-source-netlist.xml new file mode 100644 index 0000000..1af2293 --- /dev/null +++ b/hardware/PCB/validation/pcb-source-netlist.xml @@ -0,0 +1,604 @@ + + + + /home/mscholz/Repos/ESP32_serial_swiss_army_knife/hardware/PCB/serial-carrier.kicad_sch + 2026-09-20T23:07:27 + Eeschema 10.0.6-1.fc44 + + + ESP32 Serial Swiss Army Knife - Module Carrier + + A0 DRAFT + 2026-09-20 + serial-carrier.kicad_sch + + + + + + + + + + + + + + + 128x64 I2C OLED / 0x3C + Carrier:OLED_26mm_I2C_Provisional + + Module outline/header/display user fit-verified; pad/drill fit provisional + Carrier:OLED_26mm_I2C_Provisional + + + + + + + + + 0ae411c1-94cc-5551-9037-1d59c01a8ee5 + + + + + + + + + + + + + 2.2k 1% + Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal + + At least 0.125 W; exact resistor MPN pending + Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal + + + + + + + + + defb78eb-632f-5f9d-a59d-dffbb1d31dec + + + + + + + + + + + 2.2k 1% + Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal + + At least 0.125 W; exact resistor MPN pending + Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal + + + + + + + + + 405055c0-35ab-5334-ad4d-30d45c5ef6f2 + + + + + + + + + + + 2.2k 1% + Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal + + At least 0.125 W; exact resistor MPN pending + Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal + + + + + + + + + 78f9a74f-5d91-5687-b50e-68176333df23 + + + + + + + + + + + B3F-1000 + Button_Switch_THT:SW_TH_Tactile_Omron_B3F-100x + + Omron + B3F-1000 + Previous / back + Live stock not verified + Button_Switch_THT:SW_TH_Tactile_Omron_B3F-100x + + + + + + + + + + + + dd5f1f75-0093-55fc-9814-437ed26871eb + + + + + + + + + + + B3F-1000 + Button_Switch_THT:SW_TH_Tactile_Omron_B3F-100x + + Omron + B3F-1000 + Select / confirm + Live stock not verified + Button_Switch_THT:SW_TH_Tactile_Omron_B3F-100x + + + + + + + + + + + + c522a716-55a4-584d-a12e-ab135b4c08eb + + + + + + + + + + + B3F-1000 + Button_Switch_THT:SW_TH_Tactile_Omron_B3F-100x + + Omron + B3F-1000 + Next + Live stock not verified + Button_Switch_THT:SW_TH_Tactile_Omron_B3F-100x + + + + + + + + + + + + 35caa6bb-42a6-512c-848c-f1e4457aa97f + + + + + + + + + + + HW678 / S3-N16R8 + Carrier:HW678_2x22_Provisional + + Header geometry nominal; outline/antenna clearance pending + Left 1-22; right 23-44; both top-to-bottom, antenna up + Carrier:HW678_2x22_Provisional + + + + + + + + + + 3ab265d0-7fd3-5891-94eb-d39426c6a8a3 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Adafruit MAX3243 / male 6253 + + VERIFY male header numbering; footprint intentionally unassigned + adafruit-research.md; reference female 5988 CAD + + + + + + + + + + + 1127195e-e393-5d1d-9119-b25d10556144 + + + + + + + + + + + + + + + + + + + + + + + HW-678 V0.0.0 / N16R8 carrier interface; project numbering; onboard USB/regulator retained + + U + HW678_N16R8 + Carrier:HW678_2x22_Provisional + + HW-678 V0.0.0 / N16R8 carrier interface; project numbering; onboard USB/regulator retained + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Adafruit male 6253 intended; physical numbering from published female 5988 CAD, VERIFY MALE + + U + MAX3243_Module_Reference + + + Adafruit male 6253 intended; physical numbering from published female 5988 CAD, VERIFY MALE + + + + + + + + + + + + + + + + + + User fit-verified 26 mm OLED; front/top header GND VCC SCL SDA + + DS + OLED_I2C_26mm + Carrier:OLED_26mm_I2C_Provisional + + User fit-verified 26 mm OLED; front/top header GND VCC SCL SDA + + + + + + + + + + Resistor, axial DIN0207 footprint; exact MPN pending + + R + R + Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal + + Resistor, axial DIN0207 footprint; exact MPN pending + + + + + + + + Normally open contact; footprint duplicates pads 1 and 2 for internally common terminal pairs + + SW + SW_NO + Button_Switch_THT:SW_TH_Tactile_Omron_B3F-100x + + Normally open contact; footprint duplicates pads 1 and 2 for internally common terminal pairs + + + + + + + + + + ${KIPRJMOD}/Carrier.kicad_sym + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hardware/PCB/validation/pcb-validation-summary.json b/hardware/PCB/validation/pcb-validation-summary.json new file mode 100644 index 0000000..320439c --- /dev/null +++ b/hardware/PCB/validation/pcb-validation-summary.json @@ -0,0 +1,47 @@ +{ + "carrier_bounds_mm": [ + 82, + 80 + ], + "copper_layers": 2, + "draft_thickness_mm": 1.6, + "electrical_footprints": 9, + "proposed_M3_mounts": 4, + "physical_DRC_violations": 0, + "unconnected_items": 0, + "schematic_pad_nets_match": true, + "known_parity_warning": "U2 provisional female-reference footprint assigned on PCB only; schematic footprint intentionally blank", + "ignored_DRC_checks": [ + { + "description": "Footprint has no courtyard defined", + "key": "missing_courtyard" + }, + { + "description": "Track endpoint not centered on via", + "key": "track_not_centered_on_via" + }, + { + "description": "Tuning profile track geometries", + "key": "tuning_profile_track_geometries" + }, + { + "description": "Footprint doesn't match symbol's footprint filters", + "key": "footprint_filters_mismatch" + }, + { + "description": "Footprint component type doesn't match footprint pads", + "key": "footprint_type_mismatch" + } + ], + "not_validated": [ + "male module pin map/fit", + "assembly envelope and heights", + "header/socket fit", + "RF performance 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nominal; outline/antenna clearance pending + Left 1-22; right 23-44; both top-to-bottom, antenna up + Carrier:HW678_2x22_Provisional + + + + + + + + + + 3ab265d0-7fd3-5891-94eb-d39426c6a8a3 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Adafruit MAX3243 / male 6253 + + VERIFY male header numbering; footprint intentionally unassigned + adafruit-research.md; reference female 5988 CAD + + + + + + + + + + + 1127195e-e393-5d1d-9119-b25d10556144 + + + + + + + + + + + + + + + + + + + + + + + HW-678 V0.0.0 / N16R8 carrier interface; project numbering; onboard USB/regulator retained + + U + HW678_N16R8 + Carrier:HW678_2x22_Provisional + + HW-678 V0.0.0 / N16R8 carrier interface; project numbering; onboard USB/regulator retained + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Adafruit male 6253 intended; physical numbering from published female 5988 CAD, VERIFY MALE + + U + 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