# MAX3243 carrier — PROVISIONAL female CAD reference / VERIFY MALE

Footprint: `Carrier:MAX3243_Reference_Provisional` in
`Carrier.pretty/MAX3243_Reference_Provisional.kicad_mod`.
Intended only for a <=100 × 100 mm, two-copper-layer carrier PCB draft.
No schematic assignment or edits are made. This footprint does not establish
whole-board fit, connector access, DRC compliance, or fabrication readiness.

## Evidence and scope

The user reports that the male **6253** module has the same dimensions. This is
not confirmation of its pad map. Geometry below is taken from published **female
5988** Eagle CAD, not verified male-specific CAD. Confirm the purchased module's
identity, orientation, header numbering, outline and mounting geometry before
release. Never infer header order from DE-9 gender or mating-face numbering.

Source: [Adafruit PCB repository](https://github.com/adafruit/Adafruit-RS-232-Level-Shifter-Breakout-PCB),
commit `63c6200bb3ef17d491089cfa6441b1810d79bb20`.
Local original: `reference/Adafruit RS-232 Full Pinout Level-Shifter Breakout.brd`;
SHA-256 `6a7b35ef909f5a2d243c326c34db3957aaa01275bf2aac8e0c749ff18162e870`
was rechecked against the file. See `adafruit-research.md` for provenance and
female/male distinctions.

CAD-derived geometry adapted from the design by **Limor Fried/Ladyada for Adafruit
Industries**, under **CC BY-SA 3.0 Unported**:
https://creativecommons.org/licenses/by-sa/3.0/ . The CAD-derived footprint and
these CAD-derived notes use that license. Preserve the full upstream notices in
`reference/README.md` and `reference/license.txt` when redistributing this adaptation.
Changes: coordinate transformation, carrier pad convention, NPTH carrier holes,
and provisional annotations; no module circuitry or connector package copied.

## View, origin and exact nominal geometry

Front/component top view, module facing up, DE-9 toward the top (**negative Y**).
Origin is header JP2 pin 1, not a PCB corner. X increases rightward; Y downward.
Transform Eagle board coordinates in mm with:

`x = X - 1.905; y = 2.667 - Y`.

- Pads 1…12: `(2.54 × (N - 1), 0)`, first-to-last span 27.94 mm.
- Full bare-module outline is on `F.Fab`, **not carrier `Edge.Cuts`**.
  Bounds: X = -1.905…29.845, Y = -26.670…2.667 (31.750 × 29.337 mm).
  Top corners are square. Bottom corners retain the source 2.540 mm radius arcs.
- Left arc: (-1.905, 0.127) to (0.635, 2.667), centre (0.635, 0.127).
  Right arc: (27.305, 2.667) to (29.845, 0.127), centre (27.305, 0.127).
  Midpoints use radius/sqrt(2), rounded to nine decimal places in the file;
  the arcs are not chamfers or a bounding-box approximation.
- Two unnumbered **3.00 mm NPTH carrier holes**: (1.905, -8.763) and
  (26.035, -8.763), spacing 24.130 mm. These transfer module-hole centres and
  drill diameter only. The source module holes are actually plated, 3.60 mm
  copper / 3.00 mm drill, unconnected in the source signal map. Carrier NPTH
  deliberately does not copy that plating or assign electrical connections.
  No screw, washer, standoff or tool-access clearance is implied.

## Provisional carrier pads and female reference map

Same convention documented in `footprint-notes.md` for the other carrier modules:
**1.70 × 1.70 mm PTH pads / 1.00 mm drills**, rectangular pad 1, circular pads
2…12, `*.Cu` and `*.Mask`, unused copper layers retained. That convention derives
from the installed KiCad `PinHeader_1x04_P2.54mm_Vertical`; it is not a selected
header/socket qualification. The source module itself uses 1.9304 mm round pads.
Confirm actual pins/sockets, finished-hole tolerances, annular rings and assembly
height before fabrication. Square pad 1 is a carrier marker, not source evidence.

| Pad | X (mm), Y=0 | Female label | Female CAD net |
|---:|---:|---|---|
| 1 | 0.00 | Vin | VCC |
| 2 | 2.54 | GND | GND |
| 3 | 5.08 | DCD | DCD |
| 4 | 7.62 | RX | RXD |
| 5 | 10.16 | TX | TXD |
| 6 | 12.70 | DTR | DTR |
| 7 | 15.24 | DSR | DSR |
| 8 | 17.78 | RTS | RTS |
| 9 | 20.32 | CTS | CTS |
| 10 | 22.86 | RI | RI |
| 11 | 25.40 | VLD | !INVALID |
| 12 | 27.94 | OFF | !FORCEOFF |

**This is the female reference map, NOT a confirmed male map.** Footprint pads
have numbers only, no assigned nets. OFF is active low; VLD indicates valid input
when high. This project's logic interface requires 3.3 V Vin.

## Intentionally omitted / release gates

**No verified DE-9 mechanical envelope is available, so none is drawn.** No
male overhang, shell, mating plug, cable bend, enclosure cutout, height, underside
keepout, mounting-hardware clearance, 3D model or courtyard is invented. Female
library silkscreen and product bounding dimensions are not male clearance data.
The F.Fab outline describes only the bare module PCB, not the assembled envelope.
There is **no fake courtyard**; courtyard checks cannot establish assembly fit.
Short silkscreen labels identify PROVISIONAL / FEMALE CAD REF / VERIFY MALE.

Before layout release: verify male pad map and orientation against the actual
module or authoritative male CAD; perform a 1:1 fit check; select headers and
mounting hardware; verify assembled and mating envelopes; then establish real
clearances/courtyard and check the complete <=100 × 100 mm two-layer layout.

## Validation performed

KiCad **10.0.6** `pcbnew.FootprintLoad` successfully loaded the footprint using
system Python (`/usr/bin/python3 -B`) in a read-only inline check. Assertions passed
for all 12 numbered pad positions against source JP2 package/element coordinates,
female signal-contactref order, pad sizes/drills/shapes and copper/mask presence,
no assigned header nets, both NPTH centres/sizes/drills, and all six transformed
source outline segments including both 90-degree, 2.540 mm radius arcs and centres.
Also checked absence of courtyard, Edge.Cuts, zones and 3D models.

The first check assumed arc endpoint order was preserved; KiCad normalizes arc
orientation. The corrected check matches endpoint pairs independent of order and
verifies radius, angle and centre; it passed without changing geometry. The
binding emitted the same three startup `PROPERTY_ENUM` assertions documented for
other module validation; these did not prevent loading or successful checks.
No hardware fit test, male electrical verification, board DRC or firmware build
was performed. Existing `validate_footprints.py` was not changed and does not
cover this new footprint. Only this notes file and the new footprint were written;
schematic, project and lock files were left untouched.