# Provisional carrier module footprints Paths in prose point to the retained hardware artifacts or neighboring development notes. Commands keep their stated working directory; repository-root paths remain root-relative. These project-local footprints are in `../../../../hardware/PCB/Carrier.pretty`. They are mechanical starting points, **not fabrication-ready connector selections**. Both are now assigned to their matching symbols in the native schematic through the project library tables and used in the routed PCB draft. The assembled module 3D models are not provided. See `pcb-draft-notes.md` for placement/routing and `rs232-footprint-notes.md` for the additional provisional RS-232 reference footprint. ## Shared pad/drill provenance and limits Reference inspected locally: installed KiCad library footprint `Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical`, file `/usr/share/kicad/footprints/Connector_PinHeader_2.54mm.pretty/PinHeader_1x04_P2.54mm_Vertical.kicad_mod` (format version `20260206`; local KiCad `10.0.6-1.fc44`). Both footprints use that reference's **1.70 × 1.70 mm plated through-hole pads, 1.00 mm drills, rectangular pad 1, and circular remaining pads**, on `*.Cu` and `*.Mask`, with unused copper layers retained. Nominal pitch is 2.54 mm. Only the reference's pad/drill convention is reused, not its connector body, courtyard, or 3D model. HW678 pad 23 is circular: only overall pad 1 is rectangular. **PROVISIONAL connector fit — awaiting the selected actual pin/socket datasheet.** Breadboard fit supports centre spacing, not drill size, finished-hole tolerance, annular-ring suitability, socket body clearance, mating height, or solderability. Validate those against the actual final headers and beta-test sockets and the PCB fabricator's process before release. No electrical nets or ESP32 GPIO assignments are inferred. No courtyards are supplied: module/connector assembly clearances remain incomplete, so automated courtyard checks cannot establish fit. Coordinates below are millimetres, unrotated on the carrier front side, X right and Y down. Views are not mirrored. Placement on the back side or viewing the module from its solder side requires the appropriate KiCad transform; do not silently reverse the numbering. ## `Carrier:OLED_26mm_I2C_Provisional` Origin: top-left corner of the module PCB, viewed from the front/display side, header at the top. User-verified geometry from the current request and the later mechanical-evidence section of `../../../../hardware/PCB/README.md`: | Pad | Signal | X | Y | |---|---|---:|---:| | 1 | GND | 9.19 | 1.50 | | 2 | VCC | 11.73 | 1.50 | | 3 | SCL | 14.27 | 1.50 | | 4 | SDA | 16.81 | 1.50 | - PCB boundary: (0, 0) to (26, 26), solid rectangle on `F.Fab`. This depicts the module, not the carrier's routed edge; no `Edge.Cuts` is used. - Four unnumbered, non-plated through holes, diameter 2.00 mm, at (1.75, 1.75), (24.25, 1.75), (1.75, 24.25), (24.25, 24.25). Hole centres are 1.75 mm from adjacent edges, with 22.50 mm spacing in both axes. These transfer the verified module hole geometry to the carrier; they do not select screws, inserts, bosses, or hardware clearance envelopes. - Display boundary: (1, 4.5) to (25.5, 21), 24.5 × 16.5 mm, dashed on `F.Fab`. This is the supplied display boundary, not a verified active-pixel area or case cutout. - Pad-to-signal mapping is documented here and in the footprint description; footprint pads themselves have numbers, not assigned nets. The approved geometry supersedes the earlier 22.16 mm hole-spacing measurement: 22.50 mm hole spacing, Y=1.50 mm header centres, and the centred header coordinates above apply. See README for the user-reported successful template fit check. ## `Carrier:HW678_2x22_Provisional` Component/top view: antenna up, USB connectors down. Origin is the top-left header centre (pad 1), **not a PCB corner**. - Left row: pads 1 through 22, top to bottom, X=0. - Right row: pads 23 through 44, top to bottom, X=25.40. - Y=0 through 53.34 in 2.54 mm increments for each row (21 intervals). - User breadboard fit verifies nominal 2.54 mm pitch and 25.40 mm row spacing; these supersede the earlier raw caliper dimensions in README. - Numbering follows the project's explicit convention, not a generic dual-row connector's alternating or counterclockwise numbering. Physical numbers do **not** establish GPIO, supply, or ground assignments. - User-measured planar geometry is now drawn on `F.Fab`, relative to pad 1: | Feature | Start (X, Y), mm | End (X, Y), mm | |---|---|---| | Main PCB rectangle | (-1.365, -1.365) | (26.725, 54.705) | | Projecting antenna rectangle | (4.045, -8.255) | (21.675, -1.365) | | Left USB-C shell mouth span | (2.795, 54.705) | (11.665, 54.705) | | Right USB-C shell mouth span | (14.195, 54.705) | (23.065, 54.705) | Main PCB is 28.09 mm wide × 56.07 mm long; antenna projection adds 6.89 mm, giving 62.96 mm overall. Antenna left/right insets are 5.41/5.05 mm, giving 17.63 mm width and a centre 0.18 mm right of the PCB centre. Both shell widths are 8.87 mm, with outer-edge offsets 4.16 mm left / 3.66 mm right; mouths are flush with the bottom PCB edge. Lines indicate mouth spans, not shell depth. - User accepted approximate 1.365 mm top/bottom pin-centre offsets and supplied approximately the same left offset. Nominal pin pitch/row spacing are retained; resulting right margin is 1.325 mm. This 0.04 mm asymmetry follows the selected modelling datum, not a precision measurement of header asymmetry. - **No RF keepout, courtyard, full USB envelope, mounting holes or 3D model is inferred.** Shell depth/height, component/underside heights and plug clearances remain unknown. The antenna rectangle is physical geometry, not RF guidance. - Routed embedded U1 now contains the four measured F.Fab shapes and the two antenna/USB measurement-limit annotations. Generic library captions are omitted to avoid overlapping existing board labels. Existing footprint fields (including the historical hidden status/description), reference/value positions, pads, nets and UUIDs are deliberately retained; this is not a full footprint replacement. The library is authoritative for measured geometry, not those old status strings. - Measured board-local silkscreen and PDF/SVG/PNG/3D previews are refreshed. `update_u1_graphics.py` synchronizes only owned graphics, with deterministic new UUIDs and lock/concurrent-change guards; `validate_u1_update.py` checks exact preservation against the pre-update A1 snapshot. A physical 1:1 fit check is still pending; USB mouths sit 2.295 mm inside the carrier bottom edge. ## Validation and release gates Validation performed with KiCad 10.0.6 `pcbnew.FootprintLoad`: both footprints parsed successfully. Assertions passed for pad counts, all numbered pad positions, pad shapes/types/sizes/drills, OLED NPTH positions and diameters, both OLED `F.Fab` rectangle bounds, and absence of courtyards, `Edge.Cuts`, and keepout zones. The HW678 regression now checks the two measured rectangles and two USB mouth spans, while retaining exact pad geometry checks and prohibiting guessed courtyards, zones and 3D models. The local Python binding emitted three startup `PROPERTY_ENUM` assertions (also seen on a version-only import); these did not prevent loading or the checks from passing. Repeat the retained footprint regression checks from the repository root with: ```sh /usr/bin/python3 -B hardware/PCB/validate_footprints.py ``` This requires the system Python with KiCad's `pcbnew` binding. It checks the native-loaded pad counts, coordinates, pad types, sizes, drills and geometry. Parsing is not DRC, electrical verification, connector fit verification, or fabrication approval. Print both footprints at 1:1 and check the real assemblies, especially HW678 row numbering/orientation. Before layout release, select and verify connectors, map HW678 pins from reliable board evidence, and establish module envelopes, antenna restrictions, USB access, mounting hardware, and courtyards.