Commander1024/ESP32_Serial_Swiss_Army_Knife
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Add Phase 0 RS-232 characterization harness and test firmware with cli

Browse Source
This commit is contained in:
Commander1024
2026-08-22 16:15:53 +02:00
parent e43b624aec
commit 3024b135dc
11 changed files with 1164 additions and 71 deletions
Download Patch File Download Diff File Expand all files Collapse all files
wiring.md
+78
View File
@@ -88,6 +88,84 @@ The breakout's `OFF` pin is connected to the MAX3243 active-low `!FORCEOFF` inpu
GPIO8 and GPIO9 are not adjacent on the official J1 header. GPIO3 and GPIO46 lie between them and are boot-strapping pins, so follow the printed GPIO labels instead of counting header positions.
## Phase 0 loopback tests
The hardware-characterization firmware never starts a test automatically. Wire exactly one configuration below while the board is powered down, inspect the connections, power it again, and then invoke the corresponding console command.
> **Important:** DE-9 pins 3 (`TX`), 4 (`DTR`), and 7 (`RTS`) are all driven outputs. Never connect any of these three pins to another one of these output pins. Connect each output only to the receiver input specified by the selected test.
The temporary Dupont-wire breakout is mechanically fragile. Keep wires short, make all changes with power removed, and prevent loose conductors from touching neighboring pins.
### Configuration A: primary data and handshake pairs
Connect:
| From driven output | To receiver input | Expected ESP32 logic |
|---|---|---|
| DE-9 pin 3, `TX` | DE-9 pin 2, `RX` | `RX == TX` |
| DE-9 pin 4, `DTR` | DE-9 pin 6, `DSR` | `DSR == DTR` |
| DE-9 pin 7, `RTS` | DE-9 pin 8, `CTS` | `CTS == RTS` |
```text
DE-9 pin 3 TX ─────> pin 2 RX
DE-9 pin 4 DTR ─────> pin 6 DSR
DE-9 pin 7 RTS ─────> pin 8 CTS
```
Run `loopback-a`. The firmware cycles all eight TX/DTR/RTS logic combinations, waits for the MAX3243 outputs and receivers to settle, and verifies all three receiver states plus `VLD`. Two inversions occur—once in the driver and once in the receiver—so the final ESP32 logic levels must match.
Configuration A can also be used for:
- `valid-test`, with no external RS-232 peer connected.
- `uart-loopback <baud> [format] [bytes]`, although only the pin 3 to pin 2 link is needed by that command.
- `uart-suite`, again using only the pin 3 to pin 2 data link.
### Configuration B: remaining receivers
Remove all configuration A jumpers, then connect:
| From driven output | To receiver input | Expected ESP32 logic |
|---|---|---|
| DE-9 pin 3, `TX` | DE-9 pin 1, `DCD` | `DCD == TX` |
| DE-9 pin 4, `DTR` | DE-9 pin 9, `RI` | `RI == DTR` |
| DE-9 pin 7, `RTS` | DE-9 pin 2, `RX` | `RX == RTS` |
```text
DE-9 pin 3 TX ─────> pin 1 DCD
DE-9 pin 4 DTR ─────> pin 9 RI
DE-9 pin 7 RTS ─────> pin 2 RX
```
Run `loopback-b`. Together, configurations A and B exercise all three MAX3243 drivers and all five receivers.
### Manual voltage and polarity checks
With no DE-9 loopback jumpers installed, use the static `drivers` command and measure each driven output relative to DE-9 pin 5 (`GND`):
```text
drivers 0 0 0
```
Each of pins 3, 4, and 7 should be at a positive RS-232 voltage. Then run:
```text
drivers 1 1 1
```
Each output should be at a negative RS-232 voltage. Exact values vary with supply, load, meter, and charge-pump behavior; polarity is the primary check. The firmware leaves all outputs at logic 1 after automated tests.
### Recommended test order
1. Start with no DE-9 jumpers and run `status`.
2. Use `drivers 0 0 0` and `drivers 1 1 1` for the three output-polarity measurements.
3. Power down, install configuration A, power up, and run `loopback-a`.
4. With configuration A still installed and no external peer, run `valid-test`.
5. Keep only the pin 3 to pin 2 jumper and run a basic test such as `uart-loopback 9600 8N1 256`.
6. If that passes, run `uart-suite`.
7. Power down, replace the jumpers with configuration B, power up, and run `loopback-b`.
RTS/CTS hardware-flow-control behavior is intentionally deferred until these static and UART loopback tests pass. During the current UART tests, RTS and CTS remain ordinary GPIO signals and UART1 flow control is disabled.
## Future hardware profiles
Alternative boards—such as the LILYGO T-Display-S3—or different RS-232 transceivers will receive separate profiles here. GPIO assignments must be reviewed for each board's display, buttons, USB connection, flash/PSRAM wiring, boot-strapping pins, and onboard peripherals.