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Add Phase 1 UART service foundation

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Add versioned NVS-backed configuration, buffered UART1 I/O, modem
monitoring, counters, and serial console controls. Coordinate UART1
ownership with Phase 0 diagnostics and document loopback verification.
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Commander1024
2026-08-22 23:23:13 +02:00
parent 126314a277
commit 535c27350d
13 changed files with 1961 additions and 30 deletions
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wiring.md
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@@ -209,6 +209,35 @@ Each output should be at a negative RS-232 voltage. Exact values vary with suppl
RTS and CTS remain ordinary GPIO signals during static and basic UART loopback tests. Only the two dedicated flow-control commands hand them to UART peripherals. Every test shuts the MAX3243 down while changing GPIO-matrix routing and restores all outputs to static logic 1 afterward.
## Phase 1 UART-service loopback
The Phase 1 service can be checked independently of the Phase 0 UART test implementation. Disconnect external peers, power down, remove all previous jumpers, and connect only:
```text
DE-9 pin 3 TX -> pin 2 RX
```
Power up and use the default 115200 8N1 configuration:
```text
serial status
serial start
serial send-hex 0055aaff1b5b33316d
serial read 64
serial counters
serial stop
```
The read should return the exact bytes:
```text
Read 9 bytes: 0055aaff1b5b33316d
```
If the first read occurs before UART1 has returned the bytes, it may report zero; run `serial read 64` again. Counters should show nine received, queued, and sent-to-UART bytes with no dropped bytes or UART errors. `serial stop` must return the RS-232 port owner to `idle`, after which Phase 0 commands are available again.
Remove the loopback jumper with power off before connecting an external serial peer.
## Future hardware profiles
Alternative boards—such as the LILYGO T-Display-S3—or different RS-232 transceivers will receive separate profiles here. GPIO assignments must be reviewed for each board's display, buttons, USB connection, flash/PSRAM wiring, boot-strapping pins, and onboard peripherals.