Advance PCB carrier to A1 layout
Reposition the ESP32 and RS-232 reference within the notched outline, preserve the A0 snapshot, and add second-pass two-layer routing evidence. Refresh validation reports and draft previews while keeping fabrication status provisional.
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# Two-layer draft routing result
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# A1 top-left-notch / bottom-USB routing — current result
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Date: 2026-09-21. Actual revised board: `../serial-carrier.kicad_pcb`.
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**38/38 connections across 17 multi-pad nets; 0 physical DRC violations,
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0 unconnected items; exactly 1 expected U2 footprint parity warning.**
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The warning is the board-only `Carrier:MAX3243_Reference_Provisional` assignment
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versus the intentionally blank schematic footprint, not a net mismatch.
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## Geometry and preservation
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Coordinates below are local to absolute origin (100,100) mm; all dimensions mm.
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- Carrier: 82 x 80, outline `[(36,0),(82,0),(82,80),(0,80),(0,19),(36,19)]`.
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- U1 origin: (8,23), formerly (8,4). Header end-pad centres now Y=76.340;
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USB guide Y=83 is 3 mm below the bottom edge. No ESP32 body was invented.
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- U2 origin: (43,26.670), formerly (43,30). Actual reference F.Fab bare-PCB
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front edge is absolute Y=100.000, flush with carrier local Y=0.
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- Nominal male metal external dimensions are user-confirmed: shell overhang
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3.870, hex-mouth overhang 2.870, flange front 1.930 behind the carrier edge.
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With this placement their local Y positions are -3.870, -2.870 and +1.930.
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Integration added seven board-local Dwgs.User graphics for the CAD metal
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projections and screw-lock axes.
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- H1: (3.5,22.5), H2: (3.5,75). H3/H4 unchanged at (78,4)/(78,76).
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- OLED, resistors and switches unchanged.
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- RF reserve: local X=10..31 / Y=19..32, absolute X=110..131 / Y=119..132,
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both layers; no tracks, vias or fills inside it. Boundary remains provisional.
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The existing A0 board was mutated, **not regenerated**. The one-time
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`pcb-a0-before-reposition.kicad_pcb` backup remains byte-for-byte intact.
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`pcb-routing-input.kicad_pcb` is now the A1 unrouted audit input, not A0.
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`pcb-routing-preservation.py` verified all 13 complete serialized footprints
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identical except the four authorized top-level placements, including schematic
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fields, pad/net definitions, electrical UUID paths and all footprint graphics.
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Non-owned board-graphic UUIDs and unrelated graphics are preserved. ESP/RS/RF
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annotations moved with placement; the post-routing silkscreen refresh replaced
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91 owned graphics. Its edge clipping avoids silk across U2's flush front edge.
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All board saves used `SaveBoard(..., True)`. Project `.pro`, `.prl`, schematic,
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symbol/footprint libraries and library tables retain their original hashes.
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README and pcb-draft-notes were intentionally updated during integration. The generator's constants/text were updated but it was **not
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run**; its automatic project/netclass writes were removed. PCB Editor lock was
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absent at migration, routing, silkscreen refresh and final preservation check.
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## Routing and independent measurements
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- F.Cu/B.Cu; **565 segments, 22 through vias**.
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- **451 signal segments at 0.25 mm; 114 +3V3/GND segments at 0.5 mm**.
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- Vias: 0.7 mm copper / 0.3 mm drill. No copper pours needed.
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- Continuous measured minimum different-net/NPTH clearance: **0.270544 mm**.
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- Minimum copper/NPTH-to-edge gap: **1.900 mm**.
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- Minimum copper/NPTH-to-RF-reservation gap: **0.025 mm**.
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- Minimum via-drill edge to other drilled-hole edge: **0.820544 mm**.
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Two bounded passes, each with 240 seconds / 1,200,000 expansions per search:
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1. 31.18 seconds, 38/38, 674 segments / 16 vias, physical DRC clean. One GND
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connection required the router's 0.25 mm fallback; strict width validation
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correctly failed. Retained as `pcb-routing-a1-pass1.kicad_pcb` for evidence.
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2. 32.44 seconds, 38/38, 565 segments / 22 vias. Short GND connections (<=15 mm)
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now route before longer signal fanout; long GND links remain last. All power
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and ground now use 0.5 mm; no fallback. This is the saved current result.
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The grid remains 0.05 mm, physical clearance 0.25 mm plus 0.02 mm routing margin.
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No rip-up/unbounded retry or external network router was used.
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## Validation / rerun commands
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From `hardware/PCB`:
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```sh
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/usr/bin/python3 -B validate_pcb_draft.py
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/usr/bin/python3 -B validation/pcb-routing-check.py
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/usr/bin/python3 -B validation/pcb-routing-preservation.py
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kicad-cli pcb drc --format json --all-track-errors --severity-all --exit-code-violations -o validation/pcb-routing-all-drc.json serial-carrier.kicad_pcb
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```
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All passed on A1. Validators perform fresh KiCad DRC, fresh schematic-netlist
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comparison, geometry checks, continuous copper-distance checks, and routing
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save-refusal tests. DRC was read-only to preserve project settings; no copper
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zones exist to refill. Existing ignored DRC checks were not changed; see reports.
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The preservation audit includes the intentional documentation updates and seven
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CAD projection graphics while retaining electrical and project preservation checks.
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Rerouting remains explicitly destructive to existing/manual copper and requires:
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```sh
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/usr/bin/python3 -B route_pcb_draft.py --route --overwrite --replace-routes --seconds 240 --max-expansions 1200000
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/usr/bin/python3 -B add_device_silkscreen.py
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```
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Then rerun the validators. The one-shot `pcb-routing-reposition.py --apply`
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refuses anything except the original A0 snapshot and must **not** be rerun on A1.
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Current evidence: `pcb-routing-a1-pass2.log`, `pcb-routing-run.json`,
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`pcb-routing-drc.json`, `pcb-routing-all-drc.json`, `pcb-parity-drc.json`,
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`pcb-validation-summary.json`, `pcb-routing-check.json`,
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`pcb-routing-reposition.json`, and `pcb-routing-preservation.json`.
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The current post-integration board SHA-256 is recorded in
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`pcb-routing-check.json`; the CAD projection additions do not change copper.
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**Still a draft, not fabrication-ready.** ESP32 geometry/antenna/USB access,
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module pinout/header fit, full assembly/height clearances, power integrity and
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hardware operation remain unqualified. Nominal RS-232 metal dimensions alone
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are not assembly qualification. Placement PDF, SVG/PNG and carrier-only 3D
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preview were refreshed after CAD envelope integration. No Gerbers generated.
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---
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# Historical A0 routing result — superseded by A1 above
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The following records the earlier A0 routing/integration. Its dimensions, counts,
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measurements and no-save reproduction do not describe current A1. A0 `pass1`,
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`pass2`, `pass3`, `baseline` and `dry-run` files are historical; use the A1 and
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current reports listed above.
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Date: 2026-09-20. KiCad 10.0.6; system `/usr/bin/python3`.
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