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# Hardware wiring
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This document records the GPIO assignments for the initial hardware profile. Additional profiles should use separate sections rather than treating this GPIO map as universal.
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## Profile: ESP32-S3-DevKitC-1 N16R8 with Adafruit MAX3243
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This profile supports:
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- An ESP32-S3-DevKitC-1-compatible board with an ESP32-S3-WROOM-1-N16R8 module, 16 MB flash, 8 MB octal PSRAM, two USB-C ports, and an onboard RGB LED on GPIO48.
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- The [Adafruit RS-232 Full Pinout Level-Shifter Breakout](https://www.adafruit.com/product/5988), which uses a MAX3243 and has a DE-9 connector.
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Both the male and female Adafruit breakout versions can be used. Prefer the male breakout because it is the cleaner arrangement for the intended cable topology. A female breakout usually needs a gender changer; use a straight-through changer only to change connector gender, not to cross signals.
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The breakout provides three logic-to-RS-232 drivers (`TX`, `RTS`, and `DTR`), five RS-232-to-logic receivers (`RX`, `CTS`, `DSR`, `DCD`, and `RI`), valid-signal detection, and shutdown control. It is a level shifter, not a galvanic isolator.
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### Wiring table
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| Adafruit breakout pin | Direction at ESP32 | ESP32-S3 connection | DevKit header | Purpose |
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|---|---:|---:|---:|---|
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| `Vin` | Power | `3V3` | J1-1 or J1-2 | Power the MAX3243 with 3.3 V logic levels |
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| `GND` | Power | `GND` | J1-22 | Common logic and RS-232 signal ground |
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| `TX` | ESP32 → breakout | GPIO17 | J1-10 | UART1 transmit |
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| `RX` | Breakout → ESP32 | GPIO18 | J1-11 | UART1 receive |
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| `RTS` | ESP32 → breakout | GPIO15 | J1-8 | UART1 hardware receive-flow-control output |
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| `CTS` | Breakout → ESP32 | GPIO16 | J1-9 | UART1 hardware transmit-flow-control input |
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| `DTR` | ESP32 → breakout | GPIO7 | J1-7 | Software-controlled data-terminal-ready output |
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| `DSR` | Breakout → ESP32 | GPIO5 | J1-5 | Data-set-ready input |
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| `DCD` | Breakout → ESP32 | GPIO4 | J1-4 | Carrier-detect input |
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| `RI` | Breakout → ESP32 | GPIO6 | J1-6 | Ring-indicator input |
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| `VLD` | Breakout → ESP32 | GPIO8 | J1-12 | Valid RS-232 voltage indication |
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| `OFF` | ESP32 → breakout | GPIO9 | J1-15 | Optional active-low transceiver shutdown |
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Use the GPIO labels printed on a compatible development board; physical header numbering may differ from the official DevKitC-1 documentation.
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### Wiring diagram
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Arrows show signal direction at the breakout's 3.3 V logic header.
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```text
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ESP32-S3-DevKitC-1 N16R8 Adafruit MAX3243 breakout
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──────────────────────── ──────────────────────────
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3V3 ────────────> Vin
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GND ────────────> GND
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GPIO17 / U1TXD ────────────> TX
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GPIO18 / U1RXD <──────────── RX
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GPIO15 / U1RTS ────────────> RTS
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GPIO16 / U1CTS <──────────── CTS
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GPIO7 ────────────> DTR
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GPIO5 <──────────── DSR
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GPIO4 <──────────── DCD
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GPIO6 <──────────── RI
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GPIO8 <──────────── VLD
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GPIO9 ────────────> OFF
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```
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### UART and flow control
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UART1 is the external RS-232 data path. GPIO17 and GPIO18 are the ESP32-S3's conventional `U1TXD` and `U1RXD` pins. GPIO15 and GPIO16 are routed to UART1 RTS and CTS through the GPIO matrix, so their fixed-function labels do not constrain this use.
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UART0 logging remains on GPIO43 and GPIO44 through the board's USB-to-UART bridge. GPIO19 and GPIO20 are reserved for native USB CDC-ACM. When RTS/CTS flow control is enabled, the UART peripheral handles it in hardware; when disabled, firmware places the signals in compatible idle states.
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### Modem-control signals
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GPIO4 through GPIO7 provide modem-control lines:
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- GPIO4 reads `DCD`.
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- GPIO5 reads `DSR`.
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- GPIO6 reads `RI`.
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- GPIO7 drives `DTR`.
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`DCD`, `DSR`, and `RI` are GPIO inputs monitored by the firmware. `DTR` is a software-controlled GPIO output. `VLD` on GPIO8 indicates that the MAX3243 sees a valid RS-232 voltage on at least one receiver; it is a connection hint, not proof of correct cabling or serial settings.
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The breakout's `OFF` pin drives the MAX3243 active-low `!FORCEOFF` input. High or unconnected enables the transceiver; low forces shutdown. Its onboard pull-up makes it safe to leave unconnected during initial testing. If controlled by firmware, GPIO9 should be open-drain: released to enable and driven low to disable.
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### Power and cable notes
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- Connect breakout `Vin` to `3V3`, never `5V`; ESP32-S3 GPIOs are not 5 V tolerant.
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- The MAX3243 generates the positive and negative RS-232 voltages on the DE-9 side.
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- The breakout is not isolated: ESP32 ground, breakout ground, USB ground, and DE-9 pin 5 are electrically connected.
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- The breakout is DTE-style: `TX`, `RTS`, and `DTR` drive the DE-9; `RX`, `CTS`, `DSR`, `DCD`, and `RI` receive from it.
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- Use a straight-through cable for a DCE peer and a suitable null-modem cable for another DTE peer.
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- A female breakout can be used with a male-to-male straight-through gender changer. The changer changes physical gender only; it does not replace a null-modem cable where signal crossing is required.
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GPIO8 and GPIO9 are not adjacent on the official J1 header. GPIO3 and GPIO46 lie between them and are boot-strapping pins, so follow the printed GPIO labels rather than counting header positions.
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### Development and native USB connectors
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| DevKit connector | ESP32-S3 path | Typical Linux device | Purpose |
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|---|---|---|---|
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| `USB-to-UART` | UART0 on GPIO43/44 through the bridge chip | `/dev/ttyUSB*` | Firmware upload, logs, and `serial-tool>` console |
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| `USB` | Native USB OTG, GPIO19 `D-` and GPIO20 `D+` | `/dev/ttyACM*` | CDC-ACM client connected to the session broker |
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GPIO19 and GPIO20 must not be assigned to the MAX3243 or other peripherals while USB CDC is enabled. Both connectors may be attached during testing, but compatible clones can differ in connector labels and power-path design; consult the board schematic to avoid back-powering.
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The USB-to-UART bridge's DTR/RTS controls serve automatic boot/reset and do not reveal whether a terminal is open. After an unattended boot, press Enter once in an ANSI-capable terminal to enable enhanced console editing.
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Native USB CDC DTR controls the lifetime of the `usb-cdc` broker client but is not forwarded to physical DE-9 DTR. Physical DTR follows the `serial` configuration. CDC RTS is status information only; GPIO15/DE-9 RTS remains UART1 receive flow control when `flow=rts-cts` is enabled.
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## Electrical verification
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See [Electrical tests](electrical_tests.md) for safe loopback wiring, polarity checks, UART flow-control verification, and session-broker loopback testing.
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## Future hardware profiles
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Alternative boards—such as the LILYGO T-Display-S3—or different RS-232 transceivers require separate profiles. Review display, buttons, USB, flash/PSRAM wiring, boot-strapping pins, and onboard peripherals before assigning GPIOs.
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