Restructure project documentation
Separate operator guides from development contracts, relocate implementation notes under `docs/devel/`, and update cross-references and hardware tooling paths. Add getting-started, user administration, and firmware update guides while preserving firmware behavior.
This commit is contained in:
@@ -0,0 +1,145 @@
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# Adafruit MAX3243 breakout: authoritative CAD header research
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Paths in prose point to the retained hardware artifacts or neighboring development notes.
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Commands keep their stated working directory; repository-root paths remain root-relative.
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Research date: 2026-09-20. Scope: source retrieval and pad/geometry extraction only; no project schematic or layout modified.
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## Critical product distinction
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**Product 5988 is the DE-9 female version. The male version is product 6253.** The product-5988 page's male variant link goes to `/product/6253`; each product description explicitly identifies its connector gender. Both link to the same Learn guide. Do not describe the downloaded CAD as verified male-specific CAD: its connector is `X2`, value `DE9-F`, package `F09HP`, and the repository README identifies product 5988.
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The exact header map below is proven for the published 5988 board. It is useful reference for the family, but identical male-board geometry/pad numbering has **not** been established by a male-specific CAD file or physical measurement. Confirm the actual 6253 module before releasing a male carrier footprint. No inference from connector gender or a generic DE-9 footprint is substituted for that check.
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## Provenance and downloaded originals
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Authoritative chain:
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1. [Adafruit Learn downloads](https://learn.adafruit.com/adafruit-rs-232-full-pinout-level-shifter-breakout/downloads) links to the Eagle repository below, a TI datasheet, fab print and 3D models.
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2. [Adafruit PCB repository](https://github.com/adafruit/Adafruit-RS-232-Level-Shifter-Breakout-PCB).
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3. Retrieved `main` commit **`63c6200bb3ef17d491089cfa6441b1810d79bb20`**, committed 2024-08-12T22:42:27Z. All four local originals were downloaded from this immutable revision, not a moving branch.
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4. [Product 5988, female](https://www.adafruit.com/product/5988), [product 6253, male](https://www.adafruit.com/product/6253), and [Learn pinouts](https://learn.adafruit.com/adafruit-rs-232-full-pinout-level-shifter-breakout/pinouts) corroborate identity and signal names.
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Local files in `../../../../hardware/PCB/reference`, unchanged upstream contents:
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| File | SHA-256 |
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|---|---|
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| `Adafruit RS-232 Full Pinout Level-Shifter Breakout.brd` | `6a7b35ef909f5a2d243c326c34db3957aaa01275bf2aac8e0c749ff18162e870` |
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| `Adafruit RS-232 Full Pinout Level-Shifter Breakout.sch` | `4efbbe0ad14194e4e4563dd5f7dac007dfd52eba636f7390ffb822f3e81cd896` |
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| `../../../../hardware/PCB/reference/README.md` | `2825ba741a8ce83abdaf2c7cb9170641473357630ccbee40a0016dcdb5cd80bb` |
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| `license.txt` | `075dad5e5fc96c27014fabc269f4f5732909cffd178a486f546d982b6cf86b74` |
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Raw URL prefix for each filename (URL-encode spaces):
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`https://raw.githubusercontent.com/adafruit/Adafruit-RS-232-Level-Shifter-Breakout-PCB/63c6200bb3ef17d491089cfa6441b1810d79bb20/`
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**License:** upstream `license.txt` is **Creative Commons Attribution-ShareAlike 3.0 Unported (CC BY-SA 3.0)**. README attribution: “Designed by Limor Fried/Ladyada for Adafruit Industries.” README explicitly requires all its preceding text in redistribution; the full original README and license are therefore retained. Preserve these notices when redistributing CAD and comply with applicable attribution/share-alike obligations for adaptations. The CAD-derived content of this report is attributed to that design and provided under CC BY-SA 3.0.
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The guide also links [5988 3D CAD](https://github.com/adafruit/Adafruit_CAD_Parts/tree/main/5988%20RS-232%20Level%20Shifter). Its directory listing contains `.f3d`, `.step`, `.stl`, and `.jpg`; these were **not downloaded or used for measurements**, and their licensing was not independently assessed. No male-specific 3D model was verified in this research.
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## Exact header numbering and net map
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Source: Eagle XML `drawing/board/elements/element[@name='JP2']`, embedded `microbuilder` package `1X12_ROUND_76MIL`, and `drawing/board/signals/signal/contactref`. Cross-checked against schematic `JP2`, deviceset `HEADER-1X12`, selected device `76MIL`: symbol pin N maps directly to physical pad N.
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**Viewing convention:** component/top view, DE-9 pointing toward the top of the page (+Y), logic header along the bottom. X increases rightward, Y upward. The origin is the lower-left bounding-box corner of the bare PCB (the corner itself is rounded). These are Eagle board coordinates in **millimetres**, not a mating-face view and not a bottom view.
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```text
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DE-9 / +Y
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+-----------------------+
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| |
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| o o | module mounting holes
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| |
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| 1 2 3 ... 12 | JP2, y = 2.667 mm
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+-----------------------+
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Vin OFF
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+X ->
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```
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| JP2 physical pad | Label / function | CAD net | X (mm) | Y (mm) | MAX3243 IC1 pad | DE-9 X2 pad via level shifter |
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|---:|---|---|---:|---:|---:|---:|
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| 1 | Vin | VCC | 1.905 | 2.667 | 26 | — |
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| 2 | GND | GND | 4.445 | 2.667 | 25 | 5 (direct ground) |
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| 3 | DCD | DCD | 6.985 | 2.667 | 15 | 1 |
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| 4 | RX | RXD | 9.525 | 2.667 | 16 | 2 |
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| 5 | TX | TXD | 12.065 | 2.667 | 13 | 3 |
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| 6 | DTR | DTR | 14.605 | 2.667 | 14 | 4 |
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| 7 | DSR | DSR | 17.145 | 2.667 | 17 | 6 |
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| 8 | RTS | RTS | 19.685 | 2.667 | 12 | 7 |
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| 9 | CTS | CTS | 22.225 | 2.667 | 19 | 8 |
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| 10 | RI | RI | 24.765 | 2.667 | 18 | 9 |
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| 11 | VLD | !INVALID | 27.305 | 2.667 | 21 | — |
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| 12 | OFF | !FORCEOFF | 29.845 | 2.667 | 22 | — |
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**Left-to-right order: `Vin GND DCD RX TX DTR DSR RTS CTS RI VLD OFF`.** This is physical pad order, not the order of rows in the project's wiring table.
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At the logic header, TX/DTR/RTS are inputs to the MAX3243; RX/DCD/DSR/CTS/RI are outputs from it. Schematic gates explicitly map TX to T2IN, DTR to T1IN, RTS to T3IN, RX to R4OUT, DCD to R5OUT, DSR to R3OUT, CTS to R1OUT and RI to R2OUT. RS-232 and logic signal nets are separated by the chip; matching signal names do not mean direct continuity.
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OFF is **active low** (`!FORCEOFF`, IC1 pad 22) with 10 kΩ pull-up R1 to VCC. The Learn pinout page agrees. The upstream README and shop prose incorrectly say high shuts it down; do not propagate that prose error. VLD is `!INVALID`, high on valid input detection. Use 3.3 V Vin for this project's ESP32 interface, as already required by `docs/wiring.md`.
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## Exact published PCB geometry
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All figures below are nominal CAD dimensions, not measured tolerances.
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### Logic header JP2
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- Single row, **12 plated through-hole pads at 2.54 mm (0.100 inch) pitch**.
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- Element origin `(15.875, 2.667)`; no element rotation or mirroring (R0).
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- Package local pad centres: `x = -13.970 + 2.540 × (N - 1)`, `y = 0`, N = 1…12.
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- Board coordinates: `x = 1.905 + 2.540 × (N - 1)`, `y = 2.667`.
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- First-to-last centre span **27.940 mm (1.100 inch)**.
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- All holes: **1.000 mm drill**, explicit **1.9304 mm (76 mil) round copper diameter**. Each pad has `rot="R90"`; that does not rotate the header row or change a round pad's outline.
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- Both end pad centres are **1.905 mm** from the corresponding vertical board edge.
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- Row is **2.667 mm (0.105 inch)** above the lower bounding-box edge.
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- No square pad-1 marker is defined by this package: identify pad 1 using Vin and the stated view, not assumed square copper.
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### Bare-board outline and mounting holes
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Source: `drawing/board/plain/wire[@layer='20']` and mounting-hole element/package definitions.
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- Bare PCB bounding box: **31.750 mm X × 29.337 mm Y** (1.250 × 1.155 inches), X = 0…31.750, Y = 0…29.337.
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- Straight top edge `(0,29.337)` to `(31.750,29.337)`; square top corners.
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- Bottom corners: **2.540 mm radius**, defined by 90° arcs `(0,2.540)` → `(2.540,0)` and `(29.210,0)` → `(31.750,2.540)`.
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- Bottom straight edge: X = 2.540…29.210 at Y = 0.
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- Module mounting holes: `U$2` at **(3.810, 11.430)** and `U$3` at **(27.940, 11.430)**.
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- Both use `MOUNTINGHOLE_3.0_PLATEDTHIN`, pad `P$1`, **3.000 mm drill / 3.600 mm copper diameter**. They are plated pads, not anonymous NPTH holes, and neither appears in the board's signal contactrefs.
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- Hole centre spacing **24.130 mm (0.950 inch)**; hole row is **8.763 mm** above the header row.
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For a carrier footprint using header pad 1 as `(0,0)` with Y still upward:
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- Header pads: `(2.540 × (N - 1), 0)`.
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- Mounting hole centres: **(1.905, 8.763)** and **(26.035, 8.763)**.
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- Bare-board bounding box: X = **−1.905…29.845**, Y = **−2.667…26.670**; retain corner arcs described above.
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If the destination CAD uses screen coordinates with Y downward, transform Y deliberately; do not silently mirror physical pad numbering. The placement side and whether the module faces up or down must be fixed before generating a carrier footprint.
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### DE-9 on the downloaded female CAD (not male qualification)
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`X2` origin `(15.875,17.907)`, R0, package `F09HP`, value `DE9-F`.
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| X2 pad | Board X (mm) | Board Y (mm) | CAD net |
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|---|---:|---:|---|
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| 1 | 10.3886 | 16.637 | RS_DCD |
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| 2 | 13.1318 | 16.637 | RS_RXD |
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| 3 | 15.8750 | 16.637 | RS_TXD |
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| 4 | 18.6182 | 16.637 | RS_DTR |
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| 5 | 21.3614 | 16.637 | GND |
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| 6 | 11.7602 | 19.177 | RS_DSR |
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| 7 | 14.5034 | 19.177 | RS_RTS |
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| 8 | 17.2466 | 19.177 | RS_CTS |
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| 9 | 19.9898 | 19.177 | RS_RI |
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| G1 | 3.3528 | 17.907 | no signal contactref |
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| G2 | 28.3972 | 17.907 | no signal contactref |
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Signal holes have 1.016 mm drill and 1.778 mm octagonal copper; shell/mechanical pads G1/G2 have 3.302 mm drill and 5.080 mm copper, spaced 25.0444 mm. Shell pads are not shown tied to GND by signal contactrefs; DE-9 pin 5 is grounded. These are **PCB solder-tail coordinates**, not front-face pin coordinates.
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The connector package's layer-21 drawing reaches local Y = 17.907, hence board Y = 35.814, beyond the board's Y = 29.337. This is library drawing evidence, **not a validated mechanical envelope**. Do not size an enclosure from silkscreen. Product pages list assembled dimensions of 33.6 × 32.0 × 14.1 mm (5988) and 33.7 × 31.8 × 14.2 mm (6253), with no coordinate/tolerance definition; these do not replace a male-specific mechanical drawing, and differ from the female library drawing extent.
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## Validation and next-use boundary
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- Parsed the actual Eagle board and schematic XML successfully using Python's standard-library XML parser.
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- Joined package pad names to board signal contactrefs, applied JP2's unrotated element translation, and cross-checked schematic header numbering/net assignments.
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- Extracted outline arcs, mounting-hole package dimensions, and connector pad data directly; no dimensions inferred from product photos.
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- Recorded SHA-256 hashes of the downloaded originals.
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- No firmware build or hardware tests performed: this task changed research/reference files only.
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- **Ready:** exact published 5988 header map, pad centres, board outline and hole coordinates for CAD reference.
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- **Still required for a male-module carrier release:** establish that the purchased module is 6253, verify its header order and mounting geometry against male-specific CAD or the physical module, and verify connector overhang, mating clearance, module height and mounting orientation. The shared guide alone is insufficient proof of identical male geometry.
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@@ -0,0 +1,110 @@
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# Button selection: Omron B3F-1000
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Paths in prose point to the retained hardware artifacts or neighboring development notes.
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Commands keep their stated working directory; repository-root paths remain root-relative.
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Verified 2026-09-20 against the Omron datasheet and installed KiCad libraries. This research covers three active-low GPIO-to-GND buttons.
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**Integration decision:** the A0 schematic now implements B3F-1000 switches with one **2.2 kΩ, 1%, at least 0.125 W external pull-up** per input. The lower-current/internal-pull-up-only discussion below records the selection rationale, not an unselected schematic option. Firmware is unchanged. Exact resistor MPN, supply tolerance/budget and stock remain release checks.
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## Schematic-ready recommendation
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**B3F-1000 fits the installed footprint mechanically and its normally-open contact topology matches the circuit. Low-current operation with internal pull-ups needs the qualification below.**
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For each of the three buttons:
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- Value / manufacturer part number: **B3F-1000**, Omron; standard silver-plated contacts, ivory flat plunger, no separate ground terminal.
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- Symbol: **`Switch:SW_Push`** (normally open, two passive pins).
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- Explicitly assign footprint: **`Button_Switch_THT:SW_TH_Tactile_Omron_B3F-100x`**. The installed symbol's default footprint field is empty.
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- Symbol pin **1 → GPIO**, symbol pin **2 → GND**. The switch is nonpolar; swapping these two nets is electrically equivalent.
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| Function | Pin 1 net | Pin 2 net |
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|---|---|---|
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| Previous/back | GPIO10 | GND |
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| Select/confirm | GPIO13 | GND |
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| Next | GPIO14 | GND |
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GPIO assignments verified in `src/board_pins.h`. The PCB README specifies normally-open buttons to GND with internal pull-ups. Released = high; pressed = low. No voltage source connects directly through the switch: any external pull-up goes through a resistor to 3.3 V.
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## Exact terminal and pad mapping
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The installed footprint has **four physical holes but only two distinct electrical pad numbers: `1,1,2,2`**, not four uniquely numbered pads. The installed `SW_Push` symbol has pin 1 at the left and pin 2 at the right in its default orientation; pin numbers are hidden by the symbol.
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Unrotated footprint, front/top view; local coordinates in mm, positive Y downward:
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```text
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6.5 mm
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KiCad pad 1 (0,0) ----------- KiCad pad 1 (6.5,0)
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Omron terminal 4 Omron terminal 3
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NO
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contact 4.5 mm
|
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Omron terminal 2 Omron terminal 1
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KiCad pad 2 (0,4.5) --------- KiCad pad 2 (6.5,4.5)
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```
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The horizontal connections above are permanent internal connections; pressing joins the two rows. Omron datasheet **page 4**, upper-left **“Terminal Arrangement/Internal Connections (Top View)”**, explicitly shows terminals **4–3 common** and **2–1 common**. This maps to KiCad's upper pair numbered 1 and lower pair numbered 2 when aligned as shown. **Omron terminal 1 is not KiCad pad 1 in this orientation.** The manufacturer's separate bottom-view numbering sketch must not be mistaken for a top view. Omron states terminal numbers are not marked on the switches. A 180° insertion swaps the two electrical sides without affecting this nonpolar circuit.
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Both pads numbered 1 receive the symbol pin-1 net; both pads numbered 2 receive pin-2's net. Do not attach a four-unique-pin symbol to this footprint without an explicit remapping. Connecting GPIO and GND to two terminals within the same common pair would permanently ground the GPIO.
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|
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The footprint sets `duplicate_pad_numbers_are_jumpers no`; do not assume PCB routing software will treat the internal metal as a routing jumper. Route/check the duplicate-pad nets normally.
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|
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## Manufacturer dimensions and ratings
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||||
|
||||
Source: Omron B3F datasheet, ordering table p. 1, ratings/operating characteristics p. 3, B3F-1000 drawing p. 4. Dimensions below are mm.
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|
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| Item | Datasheet specification |
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|---|---|
|
||||
| Body | 6 ±0.2 × 6 ±0.2 |
|
||||
| Overall height above seating plane | 4.3 ±0.2 |
|
||||
| Plunger diameter | 3.5 |
|
||||
| Terminal row spacing | 4.5 ±0.2 |
|
||||
| Formed terminal span at hole-entry region | 6.5 ±0.5 |
|
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| Maximum-width dimension shown across formed leads | 7.7 ±0.5 |
|
||||
| Lead projection below seating plane | 3.5 |
|
||||
| Lead thickness / width callouts | 0.3 / 0.7 |
|
||||
| Recommended PCB hole-centre grid | 6.5 ±0.1 × 4.5 ±0.1 |
|
||||
| Recommended PCB holes | Four, diameter 1 ±0.1; reference drawing for PCB thickness 1.6 |
|
||||
| General dimensional tolerance | ±0.4 unless otherwise specified |
|
||||
| Contact form | SPST-NO |
|
||||
| Rated resistive load, standard silver version | **1–50 mA at 3–24 VDC** |
|
||||
| Minimum applicable load | **10 µA at 1 VDC, reference value** |
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||||
| Initial contact resistance | 100 mΩ maximum |
|
||||
| Bounce | 5 ms maximum |
|
||||
| Operating force | 0.98 ±0.29 N (100 ±30 gf) |
|
||||
| Release force | 0.2 N minimum |
|
||||
| Pretravel | 0.25 +0.2/−0.1 |
|
||||
| Durability for B3F-1000, 0.98 N | 1,000,000 operations minimum |
|
||||
| Protection / washing | IP00 / washing not possible |
|
||||
|
||||
### Installed footprint comparison
|
||||
|
||||
Inspected `/usr/share/kicad/footprints/Button_Switch_THT.pretty/SW_TH_Tactile_Omron_B3F-100x.kicad_mod` (file format version `20260206`, generator version `10.0`) and `/usr/share/kicad/symbols/Switch.kicad_sym`.
|
||||
|
||||
- Hole centres: `(0,0)`, `(6.5,0)`, `(0,4.5)`, `(6.5,4.5)` — match Omron's nominal PCB grid.
|
||||
- All four plated through-hole pads: circular copper diameter **1.7**, drill **1.0**, front/back copper and mask — nominal drill matches Omron's reference hole diameter. Confirm the fabricator's finished-hole tolerance when ordering.
|
||||
- Fab body: `(0.25,-0.75)` to `(6.25,5.25)`, **6 × 6**, matching nominal body dimensions.
|
||||
- Courtyard: `(-1.1,-1.1)` to `(7.6,5.6)`, **8.7 × 6.7**. This is a library placement boundary, not an enclosure or finger-access clearance specification.
|
||||
- Footprint description specifies H4.3 mm. No physical sample fit, enclosure-height check, or independent 3D-model measurement was performed.
|
||||
|
||||
## Low-current qualification / selection decision
|
||||
|
||||
**Do not claim internal-pull-up operation meets the standard part's full rated-load range.** At 3.3 V, pull-up resistance greater than 3.3 kΩ gives less than 1 mA contact current. For illustration only, 45 kΩ would give about 73 µA; that is not a verified resistance specification for this board's GPIOs.
|
||||
|
||||
Omron's 10 µA / 1 V minimum is explicitly a **reference value**, not an unconditional low-current reliability guarantee. B3F-1000 is a reasonable prototype choice, but internal-pull-up-only contact reliability should be qualified in the intended environment and over life.
|
||||
|
||||
For a conservative silver-contact design within the stated rated load, consider **one external 2.2 kΩ pull-up to 3.3 V per button** (about 1.5 mA while pressed); verify supply/resistor tolerances and GPIO limits before adopting. This recommendation was subsequently adopted in the A0 carrier schematic; see the integration decision above. If low current is important, the datasheet also lists **B3F-1002-G** with gold contacts in the same p. 4 dimensional group, rated 100 µA–50 mA at 3–24 VDC, but with a different operating force (1.76 ±0.49 N); weak internal pull-ups are not automatically within that rated range either. It has not been selected or stock-checked here.
|
||||
|
||||
Retain firmware debouncing; a mechanical switch is not bounce-free. The device is unsealed (IP00), and the datasheet prohibits washing.
|
||||
|
||||
## Supply evidence
|
||||
|
||||
**Live stock not verified; no supply assurance.** On 2026-09-20 a request to the [DigiKey B3F-1000 product URL](https://www.digikey.com/en/products/detail/omron-electronics-inc-emc-div/B3F-1000/33150) returned HTTP 403 / an anti-bot challenge. No quantity, price, lead time, or lifecycle status could be established from that response. Confirm the exact MPN and available quantity with a distributor before BOM release; datasheet availability is not stock evidence.
|
||||
|
||||
## Evidence and remaining checks
|
||||
|
||||
- [Authoritative Omron datasheet](https://omronfs.omron.com/en_US/ecb/products/pdf/en-b3f.pdf), retrieved 2026-09-20.
|
||||
- [Local PDF](../../../../hardware/PCB/reference/button-omron-b3f.pdf).
|
||||
- [Extracted text](../../../../hardware/PCB/reference/button-omron-b3f.txt) for searching; use the PDF for drawing interpretation.
|
||||
- [Rendered page 4](../../../../hardware/PCB/reference/button-omron-b3f-page4.png), visually checked for the internal connections and dimensions.
|
||||
|
||||
Before manufacturing: validate the selected pull-up strategy against supply tolerances/budget; check ERC/net assignment and PCB DRC in the actual design; confirm finished holes, enclosure/actuator access and a sample's fit/continuity; confirm procurement. This review verifies datasheet-to-library compatibility, not a completed-board electrical or mechanical test.
|
||||
@@ -0,0 +1,136 @@
|
||||
# DE-9 mechanical reference — pinned Adafruit 5988 STEP
|
||||
|
||||
Paths in prose point to the retained hardware artifacts or neighboring development notes.
|
||||
Commands keep their stated working directory; repository-root paths remain root-relative.
|
||||
|
||||
Research: 2026-09-21. **Nominal CAD geometry, not a toleranced connector drawing or physical fit qualification.** No board, schematic, footprint, application dependency or main README changes.
|
||||
|
||||
**User-confirmed assumption:** male and female modules have identical external dimensions; use the external geometry below for mechanical planning of the male module on that basis. This is not independent male-CAD verification and **does not verify the male pin map**. The source explicitly identifies `DE9-F` / `F09HP` (5988). Do not infer contact numbering from gender, the model, or the front view.
|
||||
|
||||
## Sources, attribution and licensing
|
||||
|
||||
- User's link: https://github.com/adafruit/Adafruit_CAD_Parts/tree/main/5988%20RS-232%20Level%20Shifter
|
||||
- Pinned repository revision: **`5b8a21fb5e2e48478faf8901077be812f5224066`**, 2024-09-05, Noe Ruiz, “Adding 5988 RS-232 Level Shifter”. GitHub path history returned this as the latest change to that directory at retrieval.
|
||||
- Immutable directory: https://github.com/adafruit/Adafruit_CAD_Parts/tree/5b8a21fb5e2e48478faf8901077be812f5224066/5988%20RS-232%20Level%20Shifter
|
||||
- Unmodified originals retained in `../../../../hardware/PCB/reference/db9-cad`: STEP, upstream repository-root `../../../../hardware/PCB/reference/db9-cad/README.md`, upstream repository-root `../../../../hardware/PCB/reference/db9-cad/LICENSE`. `../../../../hardware/PCB/reference/db9-cad/sources.json` records **full immutable raw URLs and SHA-256 hashes**.
|
||||
|
||||
| Original | SHA-256 |
|
||||
|---|---|
|
||||
| `../../../../hardware/PCB/reference/db9-cad/5988 RS-232 Level Shifter.step` | `8eab9dc591a985fc987ceec2d7534e5e259263c73bebc64c0c3cd847e135906f` |
|
||||
| `../../../../hardware/PCB/reference/db9-cad/LICENSE` | `f60436644e066301d4c2e8f1f0674a157b1f60e4fd5586717b99dde255cc18cd` |
|
||||
| `../../../../hardware/PCB/reference/db9-cad/README.md` | `9ed9beac7600623b7b9bd0d02e1fdcd86610ce22966723179e6c6b618e399dce` |
|
||||
|
||||
The CAD repository root license is **MIT, Copyright (c) 2016 Adafruit Industries**; root README merely describes STEP/Fusion/STL parts. No part-specific license file is present in the four-file directory. Retain the original MIT notice and warranty disclaimer with redistribution. This assessment follows the repository's stated license, not an independent audit of any imported vendor geometry. F3D, STL and JPG were listed but not downloaded or used; no image-derived dimensions or mesh fallback were needed.
|
||||
|
||||
The separate Eagle board reference is from `Adafruit-RS-232-Level-Shifter-Breakout-PCB`, commit `63c6200bb3ef17d491089cfa6441b1810d79bb20`; its local `.brd` hash was rechecked (`6a7b35ef909f5a2d243c326c34db3957aaa01275bf2aac8e0c749ff18162e870`). Eagle-derived registration/hole information is attributed to **Limor Fried/Ladyada for Adafruit Industries**, under **CC BY-SA 3.0 Unported**; retain `../../../../hardware/PCB/reference/README.md` and `../../../../hardware/PCB/reference/license.txt`. The Eagle-derived portions of these notes use that license. Do not silently substitute the CAD-parts repository's MIT license for the Eagle design license.
|
||||
|
||||
## Extraction method and confidence
|
||||
|
||||
Used Python/OpenCascade (`cadquery-ocp==7.9.3.1.1`) in the isolated project `.cache/cad-tools/venv`; no application dependencies changed. The initially attempted older OCP wheel was unavailable for this Python; the pinned installed version succeeded.
|
||||
|
||||
- `../../../../hardware/PCB/reference/db9-cad/extract.py`: STEPControl import with assembly placements applied; `BRepBndLib.AddOptimal` with triangulation and shape-tolerance enlargement disabled; analytic planes/cylinders via `BRepAdaptor_Surface`. No tessellation used for measurement.
|
||||
- `../../../../hardware/PCB/reference/db9-cad/geometry.json`: all 15 solids and their faces, bounds, validity, analytic cylinder radii/axes, plane normals. All 15 pass `BRepCheck_Analyzer`.
|
||||
- `../../../../hardware/PCB/reference/db9-cad/validate.py`: checks original hashes, all 12 header centres against actual Eagle XML, board bounds, mounting holes and selected front-face geometry; writes `../../../../hardware/PCB/reference/db9-cad/measurements.json` containing explicit face selections and their bounds.
|
||||
- For unique PCB/connector bodies, STEP `CLOSED_SHELL` face order is associated with import face order, checking face counts, every surface type and every cylinder radius. Appearance assignments corroborate feature identification; **colour is not a material certification**.
|
||||
- Imported solid 12 = STEP `#101` / `Body2`, the main connector. It fuses housing/insert, contacts, flange, shell and front hex posts; its whole-solid bounds are **not metal-only dimensions**. Solids 13/14 = `#102`/`#103` (`Body3`/`Body4`), separate anchor brackets.
|
||||
- Front shell/flange/hex-post faces have the shared `Opaque(245,245,246)` appearance and the expected geometric continuity. The report measures those **face subsets**, excluding plastic, contacts, PCB and ICs. There is no separate hollow metal shell solid from which to certify wall thickness.
|
||||
|
||||
**High confidence:** numerical nominal positions/bounds/radii of identified modeled features and STEP-to-Eagle board registration. **Moderate confidence:** physical fidelity of the simplified connector model and material boundaries; the contact/tail geometry differs from Eagle. **Unverified:** manufacturing tolerances, actual purchased-part fit, threads, male electrical mapping, cable/backshell envelope and final enclosure cutout. Extra decimal places below support reproducibility, not manufacturing accuracy.
|
||||
|
||||
## Coordinate system and orientation
|
||||
|
||||
All dimensions are **mm**. Use `(X,Y,Z)` in the imported STEP assembly:
|
||||
|
||||
- X rightward in component/top view; Y toward the connector/cable, Z above the PCB.
|
||||
- Bare breakout PCB: **X 0…31.750, Y 0…29.337, Z 0…1.570**. PCB front edge is **Y = 29.337**; underside is Z = 0, component-side surface Z = 1.570.
|
||||
- Logic header hole row: **Y = 2.667**, X = `1.905 + 2.540 × (N−1)`, N = 1…12. No installed header/socket body is modeled; this is the hole-axis datum, not a plastic-header edge.
|
||||
- STEP XY is already Eagle board XY: **identity transform**, no scale, rotation or translation. Verified by all 12 header holes, both mounting holes and PCB bounds. STEP connector symmetry alone would not establish this registration.
|
||||
- Existing carrier footprint coordinates (header pad 1 origin, Y downward): **`x = X − 1.905; y = 2.667 − Y`**. Height above module PCB top: **`h = Z − 1.570`**. Add the chosen module-top elevation later to get case/carrier height; socket/standoff stack is not yet selected.
|
||||
- Connector front/mating approach is along Y, **parallel to the PCB**, not down into it. A cable approaches from +Y and inserts toward −Y. A front view looks along −Y with +Z up; +X then appears to the viewer's **left**, unlike component/top view. Do not reuse top-view left/right pin numbering as front-view numbering.
|
||||
|
||||
## Metal feature dimensions — selected subsets, not assembly bounds
|
||||
|
||||
The Z centre of the D profile and front screw-lock axes is **7.84762024**, or **6.27762024 above the PCB top**. Connector centre X = **15.875** (carrier-local x = **13.970**).
|
||||
|
||||
| Feature | X bounds | Y bounds | Z bounds | Nominal dimensions / evidence |
|
||||
|---|---|---|---|---|
|
||||
| Front metal flange, exposed faces | 0.475…31.275 | 27.007…27.407 | 1.572620…14.122620 | **30.800 wide × 12.550 high × 0.400 axial thickness**; solid 12 faces 8, 11–14 |
|
||||
| D-shell straight outer wall region | 8.035981…23.714019 | 28.007…32.607 | 3.897620…11.797620 | **15.678038 wide × 7.900 high**, straight axial length **4.600**; faces 18–25 |
|
||||
| D-shell outer surface including root blend and rounded front lip | 7.435981…24.314019 | 27.407…33.207 | 3.297620…12.397620 | **16.878038 wide × 9.100 high × 5.800 axial extent**; faces 18–25, 81–88, 103–110 |
|
||||
| Left front hex screw-lock post | 0.719189…6.030811 | 27.407…32.207 | 5.547620…10.147620 | **4.600 across flats**, **5.311622 across corners**, **4.800 long**; faces 53–61, 89 |
|
||||
| Right front hex screw-lock post | 25.719189…31.030811 | 27.407…32.207 | 5.547620…10.147620 | Same dimensions; faces 62–70, 90 |
|
||||
|
||||
The flange is centred laterally on the PCB, inset **0.475** from each side. Its lower edge is only **0.002620** above the modeled PCB top, upper edge **12.552620** above it. Preserve this tiny source offset in registration; do not interpret it as a designed assembly clearance.
|
||||
|
||||
The D-shell has sloping side planes at **10° from vertical** in the front cross-section (`|normal X| = cos 10°`, `|normal Z| = sin 10°`), corner-cylinder radii **1.700**, root/lip rounding radius **0.600**. The wider side is upper (+Z). The maximum 16.878038 × 9.100 envelope occurs at the **root blend**, not uniformly along the projecting nose. These are bounding dimensions of a D shape, not a rectangular cutout prescription. Shell wall thickness / actual hollow cavity geometry is **not verified** by this fused representation.
|
||||
|
||||
### Front cable screw-lock holes: actual modeled cylinders, not thread specifications
|
||||
|
||||
- Axes **parallel to Y**, at `(X,Z) = (3.375,7.84762024)` and `(28.375,7.84762024)`.
|
||||
- **Axis spacing = 25.000**, symmetric ±12.500 about X = 15.875.
|
||||
- Carrier-local axis x = **1.470 and 26.470**; post front plane y = **−29.540**.
|
||||
- Solid 12 faces **60 / 69**, raw STEP faces **#13822 / #13831**, are inward-facing cylindrical hole surfaces: **radius 1.500, diameter 3.000**, Y = **27.407…32.007** (straight cylindrical length **4.600**).
|
||||
- Mouth cones (faces **89 / 90**) run Y = **32.007…32.207**, growing to **diameter 3.400** at the front: **0.200 axial × 0.200 radial** chamfer. Front mouth plane **Y = 32.207**.
|
||||
- Flat modeled bottoms at Y = **27.407** (faces 61/70): total modeled mouth-to-bottom depth **4.800** including chamfer.
|
||||
- **No helical threads modeled. Do not call this M3, 4-40, a tap drill, minor/major thread diameter, or usable engagement depth.** Actual screw standard, pitch, engagement and tolerances require a connector drawing or physical check.
|
||||
|
||||
## Front planes, PCB overhang and header offsets
|
||||
|
||||
There is no single interchangeable “front plane”. The flange, hex-post mouth and shell lip differ. The shell's foremost geometric plane is a useful **mating-face reference**, but the source does not establish a manufacturer's functional fully-mated datum or panel seating specification.
|
||||
|
||||
| Reference plane | STEP/Eagle Y | Forward of PCB front edge Y=29.337 | Forward of header row Y=2.667 | Carrier-local y |
|
||||
|---|---:|---:|---:|---:|
|
||||
| Flange rear face | 27.007 | −2.330 | 24.340 | −24.340 |
|
||||
| Flange front face / shell root | **27.407** | **−1.930** | **24.740** | **−24.740** |
|
||||
| Straight shell begins | 28.007 | −1.330 | 25.340 | −25.340 |
|
||||
| Breakout PCB front edge | **29.337** | 0 | **26.670** | **−26.670** |
|
||||
| Front hex-post mouth faces | **32.207** | **+2.870** | **29.540** | **−29.540** |
|
||||
| Straight shell ends / rounded lip begins | 32.607 | +3.270 | 29.940 | −29.940 |
|
||||
| Foremost shell lip / modeled insert face | **33.207** | **+3.870** | **30.540** | **−30.540** |
|
||||
|
||||
Thus the modeled shell nose projects **3.870 beyond the breakout PCB**; the hex posts project **2.870**, ending **1.000 behind the shell nose**. The flange itself is **1.930 behind the PCB front edge**. Do not position a case wall at the flange while ignoring that the PCB extends 1.930 beyond it.
|
||||
|
||||
For later unrotated, component-up carrier placement with header pad 1 at `(x0,y0)`:
|
||||
|
||||
- Breakout front edge: `y0 − 26.670`.
|
||||
- Flange front: `y0 − 24.740`.
|
||||
- Hex mouths: `y0 − 29.540`.
|
||||
- Shell nose: `y0 − 30.540`.
|
||||
- If the **breakout PCB front edge** is aligned with carrier top edge `ytop`, choose `y0 = ytop + 26.670`; shell nose is then at `ytop − 3.870`, hex mouths at `ytop − 2.870`.
|
||||
- If instead the **shell nose** is aligned with that edge, choose `y0 = ytop + 30.540`; breakout front edge is then 3.870 inward. These are different choices, not a recommended final layout.
|
||||
|
||||
## Three distinct mechanical systems — do not interchange
|
||||
|
||||
| System | Axes / coordinates | Spacing | Diameter or geometry | Purpose |
|
||||
|---|---|---:|---|---|
|
||||
| Front cable screw-lock holes | Y axes; X 3.375 / 28.375, Z 7.847620 | **25.000** | Modeled bore Ø3.000, mouth Ø3.400; no thread qualification | Retain mating cable at connector front |
|
||||
| Breakout PCB mounting holes | Z axes; `(3.810,11.430)` / `(27.940,11.430)` | **24.130** | Eagle drill Ø3.000 / plated copper Ø3.600; STEP hole cylinders Ø3.000 | Mount module to carrier/standoffs |
|
||||
| Connector shell/anchor PCB holes G1/G2 | Z axes; Eagle `(3.3528,17.907)` / `(28.3972,17.907)` | **25.0444** | Eagle drill Ø3.302 / copper Ø5.080; STEP rounds X to 3.353 / 28.397 | Receive connector anchor legs, **not** carrier mounting or cable screws |
|
||||
|
||||
### Separate metal anchor brackets and underside clearance
|
||||
|
||||
Solids **13/14** represent the bent anchor brackets/legs, not the front hex posts. Per bracket whole-solid bounds (leg-only components, not whole assembly):
|
||||
|
||||
- Right: **X 25.875…30.875, Y 17.907…24.307, Z −2.230…10.122620**.
|
||||
- Left: **X 0.875…5.875**, same Y and Z.
|
||||
- Each bracket envelope: **5.000 wide × 6.400 deep × 12.352620 high**. Bent sheet regions are **0.500 thick**; the lower two fingers occupy Y = **17.907…18.407**, not a circular screw shank.
|
||||
- Tips reach **2.230 below the module underside**, i.e. **3.800 below the module top**. This needs carrier/case underside clearance; do not turn these bounds into a mounting-hole drill recommendation.
|
||||
- Bracket symmetry centres X = **3.375 / 28.375**, lower sheet midplane Y = **18.157**. Relative to Eagle G1/G2, centre offsets are respectively **+0.0222 / −0.0222 in X** and **+0.250 in Y**. These are source-model differences, not a reason to move the Eagle pads.
|
||||
- Main fused body's signal tails separately reach Z = **−1.607380**. Their modeled rows are Y = **16.467 / 19.307**, versus Eagle **16.637 / 19.177**; horizontal pitch also differs (model 2.770 versus Eagle 2.7432). The 3D model is **not suitable as electrical pin/drill authority**.
|
||||
|
||||
No complete all-metal rear housing reconstruction is claimed: only the explicitly selected front surfaces and separate anchor brackets above. Main solid 12's 30.800 × 18.200 × 15.730 bounds include plastic/contact tails and must not be relabeled as a shell-only envelope.
|
||||
|
||||
## Validation, reproduction and release boundary
|
||||
|
||||
From project root:
|
||||
|
||||
```sh
|
||||
.cache/cad-tools/venv/bin/python -B hardware/PCB/reference/db9-cad/extract.py
|
||||
python3 -B hardware/PCB/reference/db9-cad/validate.py
|
||||
```
|
||||
|
||||
Both successfully ran; validation reported PASS for original hashes, 15 valid solids, all 12 Eagle header centres, PCB bounds, mounting holes, metal-appearance subsets and front lock cylinders. Extraction artifacts retain unrounded floating-point values. No firmware build, board DRC, hardware measurement or physical mating test was performed (research-only task).
|
||||
|
||||
**Ready for nominal placement planning:** metal flange dimensions, shell outer envelope, front hex-post dimensions and bore geometry, their distinct front planes, 25.000 front-axis spacing, PCB/header registration and overhang, anchor-leg underside extent. The A1 PCB now aligns the breakout front edge with the carrier top edge. Nominal metal bounding projections and screw-lock axes appear on Dwgs.User; companion layout/footprint notes have been updated. Neither projection nor nominal bound is an enclosure cutout or clearance qualification.
|
||||
|
||||
**Before fabrication / final case design:** verify actual male pin map; check physical connector profile and overhang against these nominal values; select header/socket and standoff heights; establish manufacturing/assembly clearances, cable backshell/tool access, wall thickness and cutout shape; verify thread standard and retention; perform a 1:1 fit/mating check. In particular, do not use exact-fit nominal bounds as an enclosure clearance or assume the CAD's Ø3.000 lock bore specifies a real screw thread.
|
||||
@@ -0,0 +1,108 @@
|
||||
# Provisional carrier module footprints
|
||||
|
||||
Paths in prose point to the retained hardware artifacts or neighboring development notes.
|
||||
Commands keep their stated working directory; repository-root paths remain root-relative.
|
||||
|
||||
These project-local footprints are in `../../../../hardware/PCB/Carrier.pretty`. They are mechanical
|
||||
starting points, **not fabrication-ready connector selections**. Both are now
|
||||
assigned to their matching symbols in the native schematic through the project
|
||||
library tables and used in the routed PCB draft. The assembled module 3D models
|
||||
are not provided. See `pcb-draft-notes.md` for placement/routing and
|
||||
`rs232-footprint-notes.md` for the additional provisional RS-232 reference footprint.
|
||||
|
||||
## Shared pad/drill provenance and limits
|
||||
|
||||
Reference inspected locally: installed KiCad library footprint
|
||||
`Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical`, file
|
||||
`/usr/share/kicad/footprints/Connector_PinHeader_2.54mm.pretty/PinHeader_1x04_P2.54mm_Vertical.kicad_mod`
|
||||
(format version `20260206`; local KiCad `10.0.6-1.fc44`).
|
||||
|
||||
Both footprints use that reference's **1.70 × 1.70 mm plated through-hole pads,
|
||||
1.00 mm drills, rectangular pad 1, and circular remaining pads**, on
|
||||
`*.Cu` and `*.Mask`, with unused copper layers retained. Nominal pitch is 2.54 mm.
|
||||
Only the reference's pad/drill convention is reused, not its connector body,
|
||||
courtyard, or 3D model. HW678 pad 23 is circular: only overall pad 1 is rectangular.
|
||||
|
||||
**PROVISIONAL connector fit — awaiting the selected actual pin/socket datasheet.**
|
||||
Breadboard fit supports centre spacing, not drill size, finished-hole tolerance,
|
||||
annular-ring suitability, socket body clearance, mating height, or solderability.
|
||||
Validate those against the actual final headers and beta-test sockets and the PCB
|
||||
fabricator's process before release. No electrical nets or ESP32 GPIO assignments
|
||||
are inferred. No courtyards are supplied: module/connector assembly clearances
|
||||
remain incomplete, so automated courtyard checks cannot establish fit.
|
||||
|
||||
Coordinates below are millimetres, unrotated on the carrier front side, X right
|
||||
and Y down. Views are not mirrored. Placement on the back side or viewing the
|
||||
module from its solder side requires the appropriate KiCad transform; do not
|
||||
silently reverse the numbering.
|
||||
|
||||
## `Carrier:OLED_26mm_I2C_Provisional`
|
||||
|
||||
Origin: top-left corner of the module PCB, viewed from the front/display side,
|
||||
header at the top. User-verified geometry from the current request and the later
|
||||
mechanical-evidence section of `../../../../hardware/PCB/README.md`:
|
||||
|
||||
| Pad | Signal | X | Y |
|
||||
|---|---|---:|---:|
|
||||
| 1 | GND | 9.19 | 1.50 |
|
||||
| 2 | VCC | 11.73 | 1.50 |
|
||||
| 3 | SCL | 14.27 | 1.50 |
|
||||
| 4 | SDA | 16.81 | 1.50 |
|
||||
|
||||
- PCB boundary: (0, 0) to (26, 26), solid rectangle on `F.Fab`.
|
||||
This depicts the module, not the carrier's routed edge; no `Edge.Cuts` is used.
|
||||
- Four unnumbered, non-plated through holes, diameter 2.00 mm, at
|
||||
(1.75, 1.75), (24.25, 1.75), (1.75, 24.25), (24.25, 24.25).
|
||||
Hole centres are 1.75 mm from adjacent edges, with 22.50 mm spacing in both axes.
|
||||
These transfer the verified module hole geometry to the carrier; they do not
|
||||
select screws, inserts, bosses, or hardware clearance envelopes.
|
||||
- Display boundary: (1, 4.5) to (25.5, 21), 24.5 × 16.5 mm, dashed on `F.Fab`.
|
||||
This is the supplied display boundary, not a verified active-pixel area or case cutout.
|
||||
- Pad-to-signal mapping is documented here and in the footprint description;
|
||||
footprint pads themselves have numbers, not assigned nets.
|
||||
|
||||
The approved geometry supersedes the earlier 22.16 mm hole-spacing measurement:
|
||||
22.50 mm hole spacing, Y=1.50 mm header centres, and the centred header coordinates
|
||||
above apply. See README for the user-reported successful template fit check.
|
||||
|
||||
## `Carrier:HW678_2x22_Provisional`
|
||||
|
||||
Component/top view: antenna up, USB connectors down. Origin is the top-left header
|
||||
centre (pad 1), **not a PCB corner**.
|
||||
|
||||
- Left row: pads 1 through 22, top to bottom, X=0.
|
||||
- Right row: pads 23 through 44, top to bottom, X=25.40.
|
||||
- Y=0 through 53.34 in 2.54 mm increments for each row (21 intervals).
|
||||
- User breadboard fit verifies nominal 2.54 mm pitch and 25.40 mm row spacing;
|
||||
these supersede the earlier raw caliper dimensions in README.
|
||||
- Numbering follows the project's explicit convention, not a generic dual-row
|
||||
connector's alternating or counterclockwise numbering. Physical numbers do
|
||||
**not** establish GPIO, supply, or ground assignments.
|
||||
- Only pads and annotation text are present. **No PCB outline, antenna keepout,
|
||||
courtyard, USB envelope, mounting holes, or 3D model is guessed.** Text positions
|
||||
are annotations, not dimensional evidence. Outline registration, antenna extent,
|
||||
connector offsets/overhang, and assembly height remain unknown.
|
||||
|
||||
## Validation and release gates
|
||||
|
||||
Validation performed with KiCad 10.0.6 `pcbnew.FootprintLoad`: both footprints
|
||||
parsed successfully. Assertions passed for pad counts, all numbered pad positions,
|
||||
pad shapes/types/sizes/drills, OLED NPTH positions and diameters, both OLED `F.Fab`
|
||||
rectangle bounds, and absence of courtyards, `Edge.Cuts`, and keepout zones.
|
||||
HW678 was also checked to contain no graphical shapes. The local Python binding
|
||||
emitted three startup `PROPERTY_ENUM` assertions (also seen on a version-only
|
||||
import); these did not prevent loading or the checks from passing.
|
||||
|
||||
Repeat the retained footprint regression checks from the repository root with:
|
||||
|
||||
```sh
|
||||
/usr/bin/python3 -B hardware/PCB/validate_footprints.py
|
||||
```
|
||||
|
||||
This requires the system Python with KiCad's `pcbnew` binding. It checks the
|
||||
native-loaded pad counts, coordinates, pad types, sizes, drills and geometry. Parsing is
|
||||
not DRC, electrical verification, connector fit verification, or fabrication approval.
|
||||
Print both footprints at 1:1 and check the real assemblies, especially HW678 row
|
||||
numbering/orientation. Before layout release, select and verify connectors, map
|
||||
HW678 pins from reliable board evidence, and establish module envelopes,
|
||||
antenna restrictions, USB access, mounting hardware, and courtyards.
|
||||
@@ -0,0 +1,246 @@
|
||||
# Compact two-layer PCB — A1 draft
|
||||
|
||||
Paths in prose point to the retained hardware artifacts or neighboring development notes.
|
||||
Commands keep their stated working directory; repository-root paths remain root-relative.
|
||||
|
||||
Open **`../../../../hardware/PCB/serial-carrier.kicad_pcb`** in KiCad 10. The routed board belongs to the
|
||||
existing `../../../../hardware/PCB/serial-carrier.kicad_pro` / `../../../../hardware/PCB/serial-carrier.kicad_sch` project. **Not for fabrication.**
|
||||
No Gerbers, production drills or manufacturing archive were generated.
|
||||
|
||||
## Size and placement
|
||||
|
||||
- **Carrier bounding dimensions: 82 × 80 mm**, within the requested 100 × 100 mm.
|
||||
- **Two copper layers**, F.Cu and B.Cu. All components mount on the front.
|
||||
- Proposed **1.6 mm** carrier thickness; fabrication stackup/process not selected.
|
||||
- Stepped outline: a **36 × 19 mm top-left antenna cutaway** fits within a simple
|
||||
rectangular/square case. The lower edge is now straight, with ESP32 USB toward
|
||||
the bottom and RS-232 toward the top. U1 moved down by 19 mm; its exact USB/body
|
||||
registration remains provisional pending the user's measured ESP32 geometry.
|
||||
- Module and mating-plug overhangs are not included in the carrier dimensions.
|
||||
The final complete assembly/enclosure envelope still needs measurement.
|
||||
|
||||
Coordinates in the following table are local millimetres from the carrier's
|
||||
upper-left corner, X right/Y down, viewed from the component side. In the KiCad
|
||||
file add (100, 100) mm to obtain absolute board coordinates. All footprints are
|
||||
unrotated; their origins are defined in the footprint notes, not necessarily
|
||||
component body corners.
|
||||
|
||||
| Reference | Local origin (X, Y) | Placement |
|
||||
|---|---|---|
|
||||
| U1 | (8, 23) | ESP32 left header pin 1; antenna toward top-left cutaway, USB toward bottom edge |
|
||||
| U2 | (43, 26.670) | MAX3243 header pin 1; bare module PCB front exactly flush with carrier top edge |
|
||||
| DS1 | (43, 36) | OLED module upper-left PCB corner; display faces up |
|
||||
| R1 / R2 / R3 | (43 / 54 / 65, 34) | Axial pull-ups in the gap between RS-232 and OLED |
|
||||
| SW1 / SW2 / SW3 | (43 / 55 / 67, 68) | Back, select, next below display; switch pad 1 origins |
|
||||
| H1 | (3.5, 22.5) | Proposed case mounting hole below antenna notch |
|
||||
| H2 | (3.5, 75) | Proposed case mounting hole near bottom-left edge |
|
||||
| H3 | (78, 4) | Proposed case mounting hole |
|
||||
| H4 | (78, 76) | Proposed case mounting hole |
|
||||
|
||||
Outline vertices: (36,0), (82,0), (82,80), (0,80), (0,19), (36,19), closed.
|
||||
The previous A0 board is retained in `../../../../hardware/PCB/validation/pcb-a0-before-reposition.kicad_pcb`.
|
||||
The board area is **58.76 cm²**; its bounding rectangle is 65.6 cm².
|
||||
|
||||
H1–H4 are proposed **Ø3.2 mm NPTH M3 clearance holes**, not a previously agreed
|
||||
case specification. They are marked board-only and excluded from the electrical
|
||||
BOM. The OLED and RS-232 module mounting holes are additional, separate holes.
|
||||
Screw heads, spacers, heat-set inserts, tool access and underside lead clearance
|
||||
must be checked against the final case and assembly heights. No insert dimensions
|
||||
or module stand-off heights are assumed.
|
||||
|
||||
## Routing and electrical status
|
||||
|
||||
The PCB contains actual copper, not just ratsnest placement:
|
||||
|
||||
- All **38 required physical-pad spanning connections** across **17 connected
|
||||
nets** routed, including both duplicated pads of each switch contact.
|
||||
- **565 segments**, signal width **0.25 mm**, 3.3 V and GND width **0.50 mm**.
|
||||
- **22 through vias**, **0.70 mm copper / 0.30 mm drill**.
|
||||
- **No copper pours**; ground is explicitly routed. This is an initial routing
|
||||
solution, not a reviewed return-current/EMI or power-integrity design.
|
||||
- Proposed minimum different-net clearance **0.25 mm** and copper-edge clearance
|
||||
**0.50 mm**. These are selected draft design rules, not fabrication qualification.
|
||||
- Project netclasses align interactive routing defaults with the draft: Default
|
||||
uses 0.25 mm tracks / 0.25 mm clearance, while Power matches `/+3V3` and `/GND`
|
||||
with 0.50 mm tracks. Both use 0.70 / 0.30 mm vias.
|
||||
- Schematic pad-net assignments, component values and UUID linkage are retained.
|
||||
U1's intentionally unused GPIO/USB/UART0/5 V header pads remain unused.
|
||||
|
||||
The bounded draft router prioritizes connectivity and conservative geometric
|
||||
clearance, not optimal trace topology. Do not treat DRC passage as evidence of
|
||||
current-carrying capacity, supply stability, I²C signal quality or EMC compliance.
|
||||
|
||||
## Explicit provisional mechanical choices
|
||||
|
||||
### ESP32 and RF
|
||||
|
||||
A two-layer **no-tracks/no-vias/no-pads/no-zone-fill rule area** reserves local
|
||||
X=10…31 mm, Y=19…32 mm beneath the antenna-side end of U1, adjacent to the notch. This is a deliberate carrier design
|
||||
allocation, **not a measured antenna envelope or a manufacturer RF keepout**.
|
||||
The module itself may span the rule area; footprint placement is not forbidden.
|
||||
No carrier copper enters the reserve, but copper runs close to its boundary.
|
||||
|
||||
U1's exact PCB/antenna/USB offsets are still unmeasured. The intended antenna
|
||||
overhang and USB access must be checked with the actual board and a printed
|
||||
placement template. Move U1, change the edge or enlarge the reserve if required.
|
||||
Missing RF clearance cannot be signed off from the current footprint alone.
|
||||
|
||||
### RS-232
|
||||
|
||||
U2 uses the new **`Carrier:MAX3243_Reference_Provisional`** footprint **on the PCB
|
||||
only**. Its bare-module outline/header/holes are adapted from published female
|
||||
5988 CAD for the intended male 6253 module. The user explicitly confirms identical
|
||||
male/female external dimensions. The linked Adafruit STEP has now been measured
|
||||
with OpenCascade; its nominal metal geometry is used on that basis. Male header
|
||||
mapping, actual fit, tolerances and the mounting stack still need qualification.
|
||||
See `rs232-footprint-notes.md` and `db9-mechanical-notes.md` for evidence/licenses.
|
||||
|
||||
The module's **bare PCB front is flush with carrier Y=0**, as requested. The
|
||||
connector has distinct front planes, not one universal case-wall datum:
|
||||
|
||||
| Feature | Position relative to carrier top edge | Meaning |
|
||||
|---|---:|---|
|
||||
| Flange front / shell root | 1.930 mm inside | Behind the PCB edge |
|
||||
| Breakout PCB front | 0 | Flush with the carrier edge |
|
||||
| Hex screw-lock mouth faces | 2.870 mm outside | Front cable-retention hole mouths |
|
||||
| Shell nose | 3.870 mm outside | Foremost modeled shell surface |
|
||||
|
||||
The front screw-lock axes are **25.000 mm apart**, with centres **6.277620 mm
|
||||
above the module PCB top**. They are not the two 24.130 mm-spaced PCB mounting
|
||||
holes. The source models Ø3.000 mm bores but **no threads**; this does not establish
|
||||
M3 or 4-40 hardware. The main metal flange is 30.800 × 12.550 × 0.400 mm; the
|
||||
shell envelope including its root/lip is 16.878 × 9.100 × 5.800 mm.
|
||||
|
||||
`../../../../hardware/PCB/add_db9_envelope.py` places the measured metal bounding projections and screw-lock
|
||||
axes on **Dwgs.User**, relative to U2. They are not silkscreen, a courtyard or a
|
||||
case cutout. Run the helper after moving U2; it preserves copper and project
|
||||
settings. The original STEP and its extraction/validation scripts are retained.
|
||||
|
||||
**Case-wall positioning remains a design decision:** PCB-edge alignment does not
|
||||
put the flange or screw-lock mouths at that same plane. For example, making the
|
||||
hex mouths flush with the case exterior would place that exterior 2.870 mm beyond
|
||||
the carrier edge. No wall thickness, cable-backshell clearance or sealing scheme
|
||||
has been assumed. The model's anchor legs extend **2.230 mm below the module
|
||||
underside**; select a stand-off/header stack or clearance solution before assembly.
|
||||
|
||||
The schematic footprint remains intentionally blank, preserving its caution
|
||||
and avoiding edits to the schematic that was open in KiCad. Consequently there
|
||||
is **one known schematic-parity warning**: U2 footprint differs from the empty
|
||||
schematic assignment. This is not excluded/suppressed, and is not a net mismatch.
|
||||
Once the male footprint is qualified, explicitly assign it in the schematic
|
||||
before relying on Update PCB from Schematic to manage U2's footprint.
|
||||
|
||||
### OLED and controls
|
||||
|
||||
OLED geometry, including its display boundary, is the user-fit-verified geometry.
|
||||
The module schematic/library files are unchanged. The new overall placement still
|
||||
needs an assembly fit check: adjacent resistor bodies, module underside parts,
|
||||
header/socket bodies, button actuation and finger/plunger clearance are not
|
||||
represented by complete assembly courtyards. In particular the axial resistors
|
||||
are tightly packed between the module outlines; confirm clearance and height.
|
||||
|
||||
## Device outlines on front silkscreen
|
||||
|
||||
The PCB now has **0.12 mm front-silkscreen outlines** for the OLED PCB and the
|
||||
published RS-232 reference module, plus a dashed OLED display boundary. The
|
||||
RS-232's visible rounded corners retain true arcs. Small gaps clear pad/mask
|
||||
openings, vias and adjacent resistor markings; the original full F.Fab geometry
|
||||
remains unchanged.
|
||||
|
||||
U1 instead has **header-row guides**, labelled `HEADER GUIDES`: guide edges are
|
||||
1.20 mm outside the outer pin centres. These are graphic alignment aids, **not
|
||||
claimed socket-body dimensions or an inferred ESP32 PCB outline**. The actual
|
||||
U1 body/antenna/USB outline still requires measured offsets. Existing button and
|
||||
resistor silkscreen remains unchanged.
|
||||
|
||||
These are board-local drawings, not edits to the footprint libraries. If the
|
||||
module placement or routing changes, close PCB Editor and refresh them with:
|
||||
|
||||
```sh
|
||||
/usr/bin/python3 -B hardware/PCB/add_device_silkscreen.py
|
||||
```
|
||||
|
||||
The script requires pcbnew and Shapely, replaces only its own generated graphics,
|
||||
and refuses an open PCB or concurrent board change. It leaves project settings,
|
||||
copper, pads and source F.Fab outlines unchanged. Run it **after** placement or
|
||||
routing regeneration; moving a footprint does not move these board-local drawings.
|
||||
It currently supports the draft's unrotated module placements.
|
||||
|
||||
The original A0 silkscreen-only change left its routing unchanged. A1 deliberately
|
||||
repositions U1/U2 and reroutes all connections, then refreshes these outlines.
|
||||
Silkscreen is clipped away from the new flush U2 front board edge. Physical DRC
|
||||
remains **0 violations**, **0 unconnected**, with the same U2 footprint-parity
|
||||
warning. PDF and both previews have been refreshed.
|
||||
|
||||
## Review outputs
|
||||
|
||||
- `../../../../hardware/PCB/validation/pcb-draft.svg` / `../../../../hardware/PCB/validation/pcb-draft.png`: combined copper/outline/fab review.
|
||||
- `../../../../hardware/PCB/validation/pcb-draft-3d.png`: KiCad render of the carrier and available standard
|
||||
component models. **ESP32, OLED and RS-232 assembled module models are absent**;
|
||||
the render is not an assembled-device or enclosure fit check.
|
||||
- `../../../../hardware/PCB/pcb-placement-draft.pdf`: **1:1** front placement/pad/outline drawing. Print at
|
||||
100%, disable fit-to-page, and confirm the outer width is 82 mm before use.
|
||||
It includes the known module outlines and nominal STEP-derived DE-9 metal
|
||||
bounding projections; no guessed U1 body or case-wall geometry.
|
||||
|
||||
## Validation and limits
|
||||
|
||||
Run from the repository root with the system Python containing KiCad bindings:
|
||||
|
||||
```sh
|
||||
/usr/bin/python3 -B hardware/PCB/validate_pcb_draft.py
|
||||
/usr/bin/python3 -B hardware/PCB/validation/pcb-routing-check.py
|
||||
```
|
||||
|
||||
The first script exports a **fresh saved-schematic netlist** and checks the actual
|
||||
PCB pad assignments, component linkage, dimensions, layer count, nominal thickness,
|
||||
mounting holes, track/via sizes and KiCad DRC. It never rewrites the PCB or project.
|
||||
It reports the single expected U2 parity warning explicitly, and fails on any
|
||||
other parity issue, DRC violation or unconnected item. Reports are retained in
|
||||
`../../../../hardware/PCB/validation/pcb-parity-drc.json` and `../../../../hardware/PCB/validation/pcb-validation-summary.json`.
|
||||
|
||||
The second independently checks continuous copper/hole/edge geometry and original
|
||||
placement/net/UUID preservation against the initial unrouted snapshot. It needs
|
||||
locally installed NumPy and Shapely in addition to pcbnew. It is not a substitute
|
||||
for current-schematic net validation and is specific to this initial layout.
|
||||
|
||||
Results with KiCad **10.0.6**:
|
||||
|
||||
- **0 physical DRC errors/warnings; 0 unconnected items.**
|
||||
- All saved-schematic pad nets match the PCB; **1 expected U2 footprint parity warning**.
|
||||
- Independent minimum different-net/copper-to-NPTH gap **0.270544 mm**; minimum
|
||||
copper/NPTH-to-board-edge gap **1.900 mm**.
|
||||
- All 9 electrical footprints and 4 board-only mounts retained; positions, outline
|
||||
and RF area revised as documented, with electrical linkage preserved.
|
||||
- Startup `PROPERTY_ENUM` assertions from the local pcbnew binding are still
|
||||
emitted, but the checks complete successfully.
|
||||
|
||||
DRC uses the existing default ignored checks: `missing_courtyard`,
|
||||
`track_not_centered_on_via`, `tuning_profile_track_geometries`,
|
||||
`footprint_filters_mismatch`, `footprint_type_mismatch`. No new exclusions were
|
||||
added to hide problems. **Missing module courtyards therefore remain an explicit
|
||||
manual release gate**. The draft rules do not represent a chosen fabricator's
|
||||
complete capability set. No electrical/hardware/fabrication tests were performed.
|
||||
|
||||
## Regeneration and project settings
|
||||
|
||||
Normal use is to **edit the native PCB in KiCad**, not regenerate it. The optional
|
||||
`../../../../hardware/PCB/generate_pcb_draft.py` recreates the *unrouted* A1 placement and discards manual
|
||||
PCB work only with explicit `--overwrite`; it refuses an open-project lock. A1 was
|
||||
made by mutating the existing board, not running that generator. All A1 saves use
|
||||
`SaveBoard(..., True)` to preserve user project settings. The original A0 creation
|
||||
populated the minimal project with rules; this revision leaves those settings and
|
||||
the schematic unchanged. Refresh device silkscreen and CAD envelope helpers after
|
||||
any intentional regeneration or placement/routing changes.
|
||||
|
||||
`../../../../hardware/PCB/route_pcb_draft.py` requires NumPy and pcbnew. By default it never saves; replacing
|
||||
existing tracks requires explicit `--route --overwrite --replace-routes`. Do not
|
||||
run that over manual routing without a backup. It is a bounded initial-draft
|
||||
router, **not** a general-purpose autorouter. See `validation/pcb-routing-summary.md`
|
||||
for algorithm limits and commands. These scripts do not need downloaded packages
|
||||
or services in the current environment and create no manufacturing outputs.
|
||||
|
||||
Before fabrication: qualify all module pin maps/footprints and connectors,
|
||||
complete assembly courtyards and RF/USB/DE-9 checks, review power/return paths,
|
||||
verify the existing USB power circuit and OLED pull-ups, confirm procurement and
|
||||
case hardware, rerun ERC/DRC, and perform an independent hardware design review.
|
||||
@@ -0,0 +1,122 @@
|
||||
# MAX3243 carrier — PROVISIONAL female CAD reference / VERIFY MALE
|
||||
|
||||
Paths in prose point to the retained hardware artifacts or neighboring development notes.
|
||||
Commands keep their stated working directory; repository-root paths remain root-relative.
|
||||
|
||||
Footprint: `Carrier:MAX3243_Reference_Provisional` in
|
||||
`../../../../hardware/PCB/Carrier.pretty/MAX3243_Reference_Provisional.kicad_mod`.
|
||||
Intended only for a <=100 × 100 mm, two-copper-layer carrier PCB draft.
|
||||
No schematic assignment or edits are made. This footprint does not establish
|
||||
whole-board fit, connector access, DRC compliance, or fabrication readiness.
|
||||
|
||||
## Evidence and scope
|
||||
|
||||
The user reports that the male **6253** module has the same dimensions. This is
|
||||
not confirmation of its pad map. Geometry below is taken from published **female
|
||||
5988** Eagle CAD, not verified male-specific CAD. Confirm the purchased module's
|
||||
identity, orientation, header numbering, outline and mounting geometry before
|
||||
release. Never infer header order from DE-9 gender or mating-face numbering.
|
||||
|
||||
Source: [Adafruit PCB repository](https://github.com/adafruit/Adafruit-RS-232-Level-Shifter-Breakout-PCB),
|
||||
commit `63c6200bb3ef17d491089cfa6441b1810d79bb20`.
|
||||
Local original: `../../../../hardware/PCB/reference/Adafruit RS-232 Full Pinout Level-Shifter Breakout.brd`;
|
||||
SHA-256 `6a7b35ef909f5a2d243c326c34db3957aaa01275bf2aac8e0c749ff18162e870`
|
||||
was rechecked against the file. See `adafruit-research.md` for provenance and
|
||||
female/male distinctions.
|
||||
|
||||
CAD-derived geometry adapted from the design by **Limor Fried/Ladyada for Adafruit
|
||||
Industries**, under **CC BY-SA 3.0 Unported**:
|
||||
https://creativecommons.org/licenses/by-sa/3.0/ . The CAD-derived footprint and
|
||||
these CAD-derived notes use that license. Preserve the full upstream notices in
|
||||
`../../../../hardware/PCB/reference/README.md` and `../../../../hardware/PCB/reference/license.txt` when redistributing this adaptation.
|
||||
Changes: coordinate transformation, carrier pad convention, NPTH carrier holes,
|
||||
and provisional annotations; no module circuitry or connector package copied.
|
||||
|
||||
## View, origin and exact nominal geometry
|
||||
|
||||
Front/component top view, module facing up, DE-9 toward the top (**negative Y**).
|
||||
Origin is header JP2 pin 1, not a PCB corner. X increases rightward; Y downward.
|
||||
Transform Eagle board coordinates in mm with:
|
||||
|
||||
`x = X - 1.905; y = 2.667 - Y`.
|
||||
|
||||
- Pads 1…12: `(2.54 × (N - 1), 0)`, first-to-last span 27.94 mm.
|
||||
- Full bare-module outline is on `F.Fab`, **not carrier `Edge.Cuts`**.
|
||||
Bounds: X = -1.905…29.845, Y = -26.670…2.667 (31.750 × 29.337 mm).
|
||||
Top corners are square. Bottom corners retain the source 2.540 mm radius arcs.
|
||||
- Left arc: (-1.905, 0.127) to (0.635, 2.667), centre (0.635, 0.127).
|
||||
Right arc: (27.305, 2.667) to (29.845, 0.127), centre (27.305, 0.127).
|
||||
Midpoints use radius/sqrt(2), rounded to nine decimal places in the file;
|
||||
the arcs are not chamfers or a bounding-box approximation.
|
||||
- Two unnumbered **3.00 mm NPTH carrier holes**: (1.905, -8.763) and
|
||||
(26.035, -8.763), spacing 24.130 mm. These transfer module-hole centres and
|
||||
drill diameter only. The source module holes are actually plated, 3.60 mm
|
||||
copper / 3.00 mm drill, unconnected in the source signal map. Carrier NPTH
|
||||
deliberately does not copy that plating or assign electrical connections.
|
||||
No screw, washer, standoff or tool-access clearance is implied.
|
||||
|
||||
## Provisional carrier pads and female reference map
|
||||
|
||||
Same convention documented in `footprint-notes.md` for the other carrier modules:
|
||||
**1.70 × 1.70 mm PTH pads / 1.00 mm drills**, rectangular pad 1, circular pads
|
||||
2…12, `*.Cu` and `*.Mask`, unused copper layers retained. That convention derives
|
||||
from the installed KiCad `PinHeader_1x04_P2.54mm_Vertical`; it is not a selected
|
||||
header/socket qualification. The source module itself uses 1.9304 mm round pads.
|
||||
Confirm actual pins/sockets, finished-hole tolerances, annular rings and assembly
|
||||
height before fabrication. Square pad 1 is a carrier marker, not source evidence.
|
||||
|
||||
| Pad | X (mm), Y=0 | Female label | Female CAD net |
|
||||
|---:|---:|---|---|
|
||||
| 1 | 0.00 | Vin | VCC |
|
||||
| 2 | 2.54 | GND | GND |
|
||||
| 3 | 5.08 | DCD | DCD |
|
||||
| 4 | 7.62 | RX | RXD |
|
||||
| 5 | 10.16 | TX | TXD |
|
||||
| 6 | 12.70 | DTR | DTR |
|
||||
| 7 | 15.24 | DSR | DSR |
|
||||
| 8 | 17.78 | RTS | RTS |
|
||||
| 9 | 20.32 | CTS | CTS |
|
||||
| 10 | 22.86 | RI | RI |
|
||||
| 11 | 25.40 | VLD | !INVALID |
|
||||
| 12 | 27.94 | OFF | !FORCEOFF |
|
||||
|
||||
**This is the female reference map, NOT a confirmed male map.** Footprint pads
|
||||
have numbers only, no assigned nets. OFF is active low; VLD indicates valid input
|
||||
when high. This project's logic interface requires 3.3 V Vin.
|
||||
|
||||
## Intentionally omitted / release gates
|
||||
|
||||
The footprint F.Fab outline still describes only the bare module PCB. Subsequent
|
||||
STEP B-rep measurements now establish nominal shell/flange/hex-post envelopes and
|
||||
registration; see `db9-mechanical-notes.md`. The user explicitly confirms identical
|
||||
male/female external dimensions. A1 board-local Dwgs.User projections show those
|
||||
nominal bounds, without changing this footprint's pads or deriving drills from
|
||||
the 3D model. Mating-plug/cable, case wall/cutout, assembly height and actual fit
|
||||
remain unqualified. No guessed complete courtyard or 3D mounting offset is added.
|
||||
There is **no fake courtyard**; courtyard checks cannot establish assembly fit.
|
||||
Short silkscreen labels identify PROVISIONAL / FEMALE CAD REF / VERIFY MALE.
|
||||
|
||||
Before layout release: verify male pad map and orientation against the actual
|
||||
module or authoritative male CAD; perform a 1:1 fit check; select headers and
|
||||
mounting hardware; verify assembled and mating envelopes; then establish real
|
||||
clearances/courtyard and check the complete <=100 × 100 mm two-layer layout.
|
||||
|
||||
## Validation performed
|
||||
|
||||
KiCad **10.0.6** `pcbnew.FootprintLoad` successfully loaded the footprint using
|
||||
system Python (`/usr/bin/python3 -B`) in a read-only inline check. Assertions passed
|
||||
for all 12 numbered pad positions against source JP2 package/element coordinates,
|
||||
female signal-contactref order, pad sizes/drills/shapes and copper/mask presence,
|
||||
no assigned header nets, both NPTH centres/sizes/drills, and all six transformed
|
||||
source outline segments including both 90-degree, 2.540 mm radius arcs and centres.
|
||||
Also checked absence of courtyard, Edge.Cuts, zones and 3D models.
|
||||
|
||||
The first check assumed arc endpoint order was preserved; KiCad normalizes arc
|
||||
orientation. The corrected check matches endpoint pairs independent of order and
|
||||
verifies radius, angle and centre; it passed without changing geometry. The
|
||||
binding emitted the same three startup `PROPERTY_ENUM` assertions documented for
|
||||
other module validation; these did not prevent loading or successful checks.
|
||||
No hardware fit test, male electrical verification, board DRC or firmware build
|
||||
was performed. Existing `../../../../hardware/PCB/validate_footprints.py` was not changed and does not
|
||||
cover this new footprint. Only this notes file and the new footprint were written;
|
||||
schematic, project and lock files were left untouched.
|
||||
@@ -0,0 +1,256 @@
|
||||
# A1 top-left-notch / bottom-USB routing — current result
|
||||
|
||||
Paths in prose point to the retained hardware artifacts or neighboring development notes.
|
||||
Commands keep their stated working directory; repository-root paths remain root-relative.
|
||||
|
||||
Date: 2026-09-21. Actual revised board: `../../../../../hardware/PCB/serial-carrier.kicad_pcb`.
|
||||
|
||||
**38/38 connections across 17 multi-pad nets; 0 physical DRC violations,
|
||||
0 unconnected items; exactly 1 expected U2 footprint parity warning.**
|
||||
The warning is the board-only `Carrier:MAX3243_Reference_Provisional` assignment
|
||||
versus the intentionally blank schematic footprint, not a net mismatch.
|
||||
|
||||
## Geometry and preservation
|
||||
|
||||
Coordinates below are local to absolute origin (100,100) mm; all dimensions mm.
|
||||
|
||||
- Carrier: 82 x 80, outline `[(36,0),(82,0),(82,80),(0,80),(0,19),(36,19)]`.
|
||||
- U1 origin: (8,23), formerly (8,4). Header end-pad centres now Y=76.340;
|
||||
USB guide Y=83 is 3 mm below the bottom edge. No ESP32 body was invented.
|
||||
- U2 origin: (43,26.670), formerly (43,30). Actual reference F.Fab bare-PCB
|
||||
front edge is absolute Y=100.000, flush with carrier local Y=0.
|
||||
- Nominal male metal external dimensions are user-confirmed: shell overhang
|
||||
3.870, hex-mouth overhang 2.870, flange front 1.930 behind the carrier edge.
|
||||
With this placement their local Y positions are -3.870, -2.870 and +1.930.
|
||||
Integration added seven board-local Dwgs.User graphics for the CAD metal
|
||||
projections and screw-lock axes.
|
||||
- H1: (3.5,22.5), H2: (3.5,75). H3/H4 unchanged at (78,4)/(78,76).
|
||||
- OLED, resistors and switches unchanged.
|
||||
- RF reserve: local X=10..31 / Y=19..32, absolute X=110..131 / Y=119..132,
|
||||
both layers; no tracks, vias or fills inside it. Boundary remains provisional.
|
||||
|
||||
The existing A0 board was mutated, **not regenerated**. The one-time
|
||||
`../../../../../hardware/PCB/validation/pcb-a0-before-reposition.kicad_pcb` backup remains byte-for-byte intact.
|
||||
`../../../../../hardware/PCB/validation/pcb-routing-input.kicad_pcb` is now the A1 unrouted audit input, not A0.
|
||||
`../../../../../hardware/PCB/validation/pcb-routing-preservation.py` verified all 13 complete serialized footprints
|
||||
identical except the four authorized top-level placements, including schematic
|
||||
fields, pad/net definitions, electrical UUID paths and all footprint graphics.
|
||||
Non-owned board-graphic UUIDs and unrelated graphics are preserved. ESP/RS/RF
|
||||
annotations moved with placement; the post-routing silkscreen refresh replaced
|
||||
91 owned graphics. Its edge clipping avoids silk across U2's flush front edge.
|
||||
|
||||
All board saves used `SaveBoard(..., True)`. Project `.pro`, `.prl`, schematic,
|
||||
symbol/footprint libraries and library tables retain their original hashes.
|
||||
README and pcb-draft-notes were intentionally updated during integration. The generator's constants/text were updated but it was **not
|
||||
run**; its automatic project/netclass writes were removed. PCB Editor lock was
|
||||
absent at migration, routing, silkscreen refresh and final preservation check.
|
||||
|
||||
## Routing and independent measurements
|
||||
|
||||
- F.Cu/B.Cu; **565 segments, 22 through vias**.
|
||||
- **451 signal segments at 0.25 mm; 114 +3V3/GND segments at 0.5 mm**.
|
||||
- Vias: 0.7 mm copper / 0.3 mm drill. No copper pours needed.
|
||||
- Continuous measured minimum different-net/NPTH clearance: **0.270544 mm**.
|
||||
- Minimum copper/NPTH-to-edge gap: **1.900 mm**.
|
||||
- Minimum copper/NPTH-to-RF-reservation gap: **0.025 mm**.
|
||||
- Minimum via-drill edge to other drilled-hole edge: **0.820544 mm**.
|
||||
|
||||
Two bounded passes, each with 240 seconds / 1,200,000 expansions per search:
|
||||
|
||||
1. 31.18 seconds, 38/38, 674 segments / 16 vias, physical DRC clean. One GND
|
||||
connection required the router's 0.25 mm fallback; strict width validation
|
||||
correctly failed. Retained as `../../../../../hardware/PCB/validation/pcb-routing-a1-pass1.kicad_pcb` for evidence.
|
||||
2. 32.44 seconds, 38/38, 565 segments / 22 vias. Short GND connections (<=15 mm)
|
||||
now route before longer signal fanout; long GND links remain last. All power
|
||||
and ground now use 0.5 mm; no fallback. This is the saved current result.
|
||||
|
||||
The grid remains 0.05 mm, physical clearance 0.25 mm plus 0.02 mm routing margin.
|
||||
No rip-up/unbounded retry or external network router was used.
|
||||
|
||||
## Validation / rerun commands
|
||||
|
||||
From `hardware/PCB`:
|
||||
|
||||
```sh
|
||||
/usr/bin/python3 -B validate_pcb_draft.py
|
||||
/usr/bin/python3 -B validation/pcb-routing-check.py
|
||||
/usr/bin/python3 -B validation/pcb-routing-preservation.py
|
||||
kicad-cli pcb drc --format json --all-track-errors --severity-all --exit-code-violations -o validation/pcb-routing-all-drc.json serial-carrier.kicad_pcb
|
||||
```
|
||||
|
||||
All passed on A1. Validators perform fresh KiCad DRC, fresh schematic-netlist
|
||||
comparison, geometry checks, continuous copper-distance checks, and routing
|
||||
save-refusal tests. DRC was read-only to preserve project settings; no copper
|
||||
zones exist to refill. Existing ignored DRC checks were not changed; see reports.
|
||||
The preservation audit includes the intentional documentation updates and seven
|
||||
CAD projection graphics while retaining electrical and project preservation checks.
|
||||
|
||||
Rerouting remains explicitly destructive to existing/manual copper and requires:
|
||||
|
||||
```sh
|
||||
/usr/bin/python3 -B route_pcb_draft.py --route --overwrite --replace-routes --seconds 240 --max-expansions 1200000
|
||||
/usr/bin/python3 -B add_device_silkscreen.py
|
||||
```
|
||||
|
||||
Then rerun the validators. The one-shot `pcb-routing-reposition.py --apply`
|
||||
refuses anything except the original A0 snapshot and must **not** be rerun on A1.
|
||||
|
||||
Current evidence: `../../../../../hardware/PCB/validation/pcb-routing-a1-pass2.log`, `../../../../../hardware/PCB/validation/pcb-routing-run.json`,
|
||||
`../../../../../hardware/PCB/validation/pcb-routing-drc.json`, `../../../../../hardware/PCB/validation/pcb-routing-all-drc.json`, `../../../../../hardware/PCB/validation/pcb-parity-drc.json`,
|
||||
`../../../../../hardware/PCB/validation/pcb-validation-summary.json`, `../../../../../hardware/PCB/validation/pcb-routing-check.json`,
|
||||
`../../../../../hardware/PCB/validation/pcb-routing-reposition.json`, and `../../../../../hardware/PCB/validation/pcb-routing-preservation.json`.
|
||||
The current post-integration board SHA-256 is recorded in
|
||||
`../../../../../hardware/PCB/validation/pcb-routing-check.json`; the CAD projection additions do not change copper.
|
||||
|
||||
**Still a draft, not fabrication-ready.** ESP32 geometry/antenna/USB access,
|
||||
module pinout/header fit, full assembly/height clearances, power integrity and
|
||||
hardware operation remain unqualified. Nominal RS-232 metal dimensions alone
|
||||
are not assembly qualification. Placement PDF, SVG/PNG and carrier-only 3D
|
||||
preview were refreshed after CAD envelope integration. No Gerbers generated.
|
||||
|
||||
---
|
||||
|
||||
# Historical A0 routing result — superseded by A1 above
|
||||
|
||||
The following records the earlier A0 routing/integration. Its dimensions, counts,
|
||||
measurements and no-save reproduction do not describe current A1. A0 `pass1`,
|
||||
`pass2`, `pass3`, `baseline` and `dry-run` files are historical; use the A1 and
|
||||
current reports listed above.
|
||||
|
||||
Date: 2026-09-20. KiCad 10.0.6; system `/usr/bin/python3`.
|
||||
|
||||
## Saved result
|
||||
|
||||
Actual copper routing is saved in `../../../../../hardware/PCB/serial-carrier.kicad_pcb`, not just a preview
|
||||
or an exported proposal. **38/38 required spanning-tree connections across 17
|
||||
multi-pad nets routed; KiCad reports 0 unconnected items, 0 errors, 0 warnings.**
|
||||
Intentional single-pad `unconnected-(...)` nets retain their original names and
|
||||
are not connected to anything else.
|
||||
|
||||
- Two copper layers, F.Cu and B.Cu.
|
||||
- 569 straight track segments: 425 at 0.25 mm for signals and 144 at 0.5 mm for
|
||||
+3V3/GND. No narrow power-track fallback was necessary.
|
||||
- 20 through vias, 0.7 mm copper diameter / 0.3 mm drill.
|
||||
- No copper pours: all ground connections were routed explicitly.
|
||||
- Original RF rule area, x110..131 / y100..113 mm on both copper layers, preserved.
|
||||
No tracks, vias or fills enter the reservation. Minimum copper-to-reservation
|
||||
gap measured independently is 0.025 mm; this is geometric compliance with the
|
||||
specified provisional boundary, **not validation of an antenna's RF needs**.
|
||||
- All 9 electrical footprints and 4 standalone mounting footprints preserved.
|
||||
Pad positions, shapes, sizes, drills, types, nets, functions, pin types and UUIDs;
|
||||
footprint placement, orientation, library IDs, values, UUIDs and schematic UUID
|
||||
paths; net table, outline and RF rule-area geometry/flags match the input.
|
||||
- Generator, README, schematic, project and libraries were not edited by routing.
|
||||
No external network dependency or manufacturing exports were used.
|
||||
|
||||
## Validation performed
|
||||
|
||||
From `hardware/PCB`:
|
||||
|
||||
```sh
|
||||
kicad-cli pcb drc --format json --refill-zones --save-board -o validation/pcb-routing-drc.json serial-carrier.kicad_pcb
|
||||
kicad-cli pcb drc --format json --all-track-errors --severity-all --exit-code-violations -o validation/pcb-routing-all-drc.json serial-carrier.kicad_pcb
|
||||
/usr/bin/python3 -B validation/pcb-routing-check.py
|
||||
```
|
||||
|
||||
Both DRC runs: **0 violations and 0 unconnected items**. No DRC settings or
|
||||
exclusions were added or changed. Existing project rules specify 0.25 mm minimum
|
||||
clearance, 0.5 mm copper-edge clearance, 0.25 mm minimum track width and 0.7 mm
|
||||
minimum via diameter.
|
||||
|
||||
Independent continuous-geometry audit (`../../../../../hardware/PCB/validation/pcb-routing-check.json`):
|
||||
|
||||
| Check | Measured minimum | Requirement |
|
||||
|---|---:|---:|
|
||||
| Different-net copper / copper-to-NPTH clearance | 0.275 mm | 0.25 mm |
|
||||
| Copper or NPTH edge to board edge | 0.525 mm | 0.5 mm |
|
||||
| Copper / NPTH edge to RF reserve | 0.025 mm | No intersection |
|
||||
| Via drill edge to another drilled hole edge | 0.840175 mm | 0.25 mm |
|
||||
|
||||
The audit uses exact straight-line/point/rectangle distance calculations with
|
||||
copper radii, rather than the router's raster masks. It also verifies dimensions,
|
||||
source-preservation invariants, and three overwrite-refusal cases. Requires
|
||||
locally installed `pcbnew`, NumPy and Shapely; the router itself only needs
|
||||
`pcbnew` and NumPy.
|
||||
|
||||
DRC still honors the project's pre-existing ignored checks:
|
||||
`missing_courtyard`, `track_not_centered_on_via`,
|
||||
`tuning_profile_track_geometries`, `footprint_filters_mismatch`, and
|
||||
`footprint_type_mismatch`. `--severity-all` does not enable ignored checks.
|
||||
The routing subtask compared electrical UUID linkage and pad-net assignments
|
||||
with the input board. Subsequent integration also ran fresh schematic-parity DRC
|
||||
and added missing symbol metadata fields to the PCB without changing copper.
|
||||
That check reports exactly one expected U2 footprint warning (provisional PCB
|
||||
footprint versus intentionally blank schematic assignment); no net mismatch.
|
||||
See `../../../../../hardware/PCB/validation/pcb-parity-drc.json` and `../../../../../hardware/PCB/validation/pcb-validation-summary.json`.
|
||||
|
||||
## Method and bounded passes
|
||||
|
||||
`../../../../../hardware/PCB/route_pcb_draft.py` uses a two-layer 8-direction raster A* search, an explicit
|
||||
via cost, exact-pad-centre terminal stubs, conservative foreign-copper and hole
|
||||
obstacles, and only collinear path compression. It preserves the L-shaped edge
|
||||
and RF reservation. Per-net minimum spanning trees connect every physical pad,
|
||||
including duplicate switch contacts; short links precede longer links and GND is
|
||||
last. It does not optimize return-current paths, topology or total via count.
|
||||
|
||||
1. Initial 0.1 mm raster / 0.04 mm safety margin / 250,000 expansions per search:
|
||||
29/38 connections; DRC 0 violations, 9 unconnected.
|
||||
2. Increased search allowance to 1,200,000 expansions: 30/38; DRC 0 violations,
|
||||
8 unconnected. Some raster header passages were blocked, not just expensive.
|
||||
3. Final 0.05 mm raster / 0.02 mm additional safety margin, with 0.25 mm physical
|
||||
clearance unchanged: 38/38 in approximately 26.5 seconds; DRC fully connected.
|
||||
Each pass had a 240-second routing deadline. No unresolved routing remains.
|
||||
|
||||
A KiCad Python binding ownership problem in the first replacement attempt caused
|
||||
an exception/segfault before any board save. Replacement now uses `board.Delete`
|
||||
instead of `board.Remove`; the subsequent save and no-save rerun both passed.
|
||||
The known startup PROPERTY_ENUM assertions do not prevent validation.
|
||||
|
||||
## Rerun safety
|
||||
|
||||
By default the script never saves. The existing routed board is protected even
|
||||
from a preview unless `--replace-routes` is given. A preview can be run with:
|
||||
|
||||
```sh
|
||||
/usr/bin/python3 -B route_pcb_draft.py --replace-routes --seconds 240
|
||||
```
|
||||
|
||||
This exact no-save workflow was tested: it again found 38/38 connections, 569
|
||||
segments and 20 vias, and left the board byte-for-byte unchanged.
|
||||
|
||||
**The following command discards all existing/manual tracks and vias**, then
|
||||
replaces them with fresh draft routing. Back up manual work first:
|
||||
|
||||
```sh
|
||||
/usr/bin/python3 -B route_pcb_draft.py --route --overwrite --replace-routes --seconds 240 --max-expansions 1200000
|
||||
```
|
||||
|
||||
The script refuses a PCB-editor lock, unexpected outline/RF/board structure,
|
||||
unsupported pad orientation/layers, unapproved existing routes, or detected board
|
||||
changes before save. Candidate serialization must preserve immutable geometry
|
||||
and linkage before replacing the board. It deliberately does not run DRC itself:
|
||||
rerun the validation commands after any routing change. Runtime/expansion limits
|
||||
can produce a partial board; inspect both the run report and actual DRC, not just
|
||||
the script exit status.
|
||||
|
||||
## Evidence and remaining limitations
|
||||
|
||||
- `../../../../../hardware/PCB/validation/pcb-routing-input.kicad_pcb`: unrouted input snapshot, after baseline DRC save.
|
||||
- `../../../../../hardware/PCB/validation/pcb-routing-baseline.json`: 38 unconnected / no violations before routing.
|
||||
- `../../../../../hardware/PCB/validation/pcb-routing-pass1-drc.json`, `../../../../../hardware/PCB/validation/pcb-routing-pass2-drc.json`: intermediate DRC.
|
||||
- `../../../../../hardware/PCB/validation/pcb-routing-pass2.log`, `../../../../../hardware/PCB/validation/pcb-routing-pass3.log`: bounded routing progress.
|
||||
- `../../../../../hardware/PCB/validation/pcb-routing-run.json`: final saved-route metrics and connection list.
|
||||
- `../../../../../hardware/PCB/validation/pcb-routing-drc.json`, `../../../../../hardware/PCB/validation/pcb-routing-all-drc.json`: final KiCad DRC evidence.
|
||||
- `../../../../../hardware/PCB/validation/pcb-routing-check.py`, `../../../../../hardware/PCB/validation/pcb-routing-check.json`: repeatable independent audit.
|
||||
- `../../../../../hardware/PCB/validation/pcb-routing-dry-run.log`: successful final no-save reproduction.
|
||||
|
||||
Routing-only DRC-saved snapshot SHA-256 (before integration copied schematic
|
||||
metadata fields): `bf94b6c9b00c43a97f933054758a2c9d6541981ae09f2f285dcdb567bd73d9b1`.
|
||||
The current post-integration hash is recorded by `../../../../../hardware/PCB/validation/pcb-routing-check.json`;
|
||||
geometry, pad-net linkage and copper are unchanged by the metadata copy.
|
||||
|
||||
**Still DRAFT / NOT FOR FABRICATION.** Provisional module/connector geometry,
|
||||
antenna envelope, assembly/courtyard clearances, USB access, male RS-232 connector
|
||||
fit, physical pin mapping, power integrity, EMI and hardware operation are not
|
||||
qualified by routing or DRC. All previously documented mechanical/electrical
|
||||
release gates remain. No physical-device or manufacturing validation performed.
|
||||
Reference in New Issue
Block a user