Integrate A1 carrier PCB CAD updates
- Add pinned STEP-derived DE-9 mechanical measurements and provenance - Refresh placement, routing, silkscreen, and nominal CAD envelopes - Document provisional dimensions, assumptions, and validation status
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@@ -83,11 +83,13 @@ when high. This project's logic interface requires 3.3 V Vin.
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## Intentionally omitted / release gates
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**No verified DE-9 mechanical envelope is available, so none is drawn.** No
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male overhang, shell, mating plug, cable bend, enclosure cutout, height, underside
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keepout, mounting-hardware clearance, 3D model or courtyard is invented. Female
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library silkscreen and product bounding dimensions are not male clearance data.
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The F.Fab outline describes only the bare module PCB, not the assembled envelope.
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The footprint F.Fab outline still describes only the bare module PCB. Subsequent
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STEP B-rep measurements now establish nominal shell/flange/hex-post envelopes and
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registration; see `db9-mechanical-notes.md`. The user explicitly confirms identical
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male/female external dimensions. A1 board-local Dwgs.User projections show those
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nominal bounds, without changing this footprint's pads or deriving drills from
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the 3D model. Mating-plug/cable, case wall/cutout, assembly height and actual fit
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remain unqualified. No guessed complete courtyard or 3D mounting offset is added.
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There is **no fake courtyard**; courtyard checks cannot establish assembly fit.
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Short silkscreen labels identify PROVISIONAL / FEMALE CAD REF / VERIFY MALE.
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