Integrate A1 carrier PCB CAD updates

- Add pinned STEP-derived DE-9 mechanical measurements and provenance
- Refresh placement, routing, silkscreen, and nominal CAD envelopes
- Document provisional dimensions, assumptions, and validation status
This commit is contained in:
2026-09-21 12:31:24 +02:00
parent 06df47c934
commit c0f7a1ad51
13 changed files with 5825 additions and 3966 deletions
+7 -5
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@@ -83,11 +83,13 @@ when high. This project's logic interface requires 3.3 V Vin.
## Intentionally omitted / release gates
**No verified DE-9 mechanical envelope is available, so none is drawn.** No
male overhang, shell, mating plug, cable bend, enclosure cutout, height, underside
keepout, mounting-hardware clearance, 3D model or courtyard is invented. Female
library silkscreen and product bounding dimensions are not male clearance data.
The F.Fab outline describes only the bare module PCB, not the assembled envelope.
The footprint F.Fab outline still describes only the bare module PCB. Subsequent
STEP B-rep measurements now establish nominal shell/flange/hex-post envelopes and
registration; see `db9-mechanical-notes.md`. The user explicitly confirms identical
male/female external dimensions. A1 board-local Dwgs.User projections show those
nominal bounds, without changing this footprint's pads or deriving drills from
the 3D model. Mating-plug/cable, case wall/cutout, assembly height and actual fit
remain unqualified. No guessed complete courtyard or 3D mounting offset is added.
There is **no fake courtyard**; courtyard checks cannot establish assembly fit.
Short silkscreen labels identify PROVISIONAL / FEMALE CAD REF / VERIFY MALE.