Record Accepted PCB Placement And Fit
Align component groups, repair affected routing, and add preservation audits. Assign the confirmed U2 footprint and update pull-ups to 2 kΩ across design files. Document user acceptance, switch to an A3 worksheet, and refresh PCB exports.
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# Button selection: Omron B3F-1000
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> **Current status (2026-09-22):** [User acceptance and group alignment](user-acceptance.md) supersedes the earlier pending user-fit, USB-clearance, male-map, procurement and mounting-hardware items below. Original research/evidence remains historical; acceptance is not independent qualification.
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Paths in prose point to the retained hardware artifacts or neighboring development notes.
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Commands keep their stated working directory; repository-root paths remain root-relative.
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Verified 2026-09-20 against the Omron datasheet and installed KiCad libraries. This research covers three active-low GPIO-to-GND buttons.
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**Integration decision:** the A0 schematic now implements B3F-1000 switches with one **2.2 kΩ, 1%, at least 0.125 W external pull-up** per input. The lower-current/internal-pull-up-only discussion below records the selection rationale, not an unselected schematic option. Firmware is unchanged. Exact resistor MPN, supply tolerance/budget and stock remain release checks.
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**Integration decision:** the A0 schematic now implements B3F-1000 switches with one **2 kΩ, 1%, metal-film external pull-up (design rating at least 0.125 W)** per input. The lower-current/internal-pull-up-only discussion below records the selection rationale, not an unselected schematic option. Firmware is unchanged. User reports B3F-1000 and resistors purchased. Exact resistor MPN/wattage and measured supply margin remain unspecified.
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## Schematic-ready recommendation
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@@ -92,7 +94,7 @@ Inspected `/usr/share/kicad/footprints/Button_Switch_THT.pretty/SW_TH_Tactile_Om
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Omron's 10 µA / 1 V minimum is explicitly a **reference value**, not an unconditional low-current reliability guarantee. B3F-1000 is a reasonable prototype choice, but internal-pull-up-only contact reliability should be qualified in the intended environment and over life.
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For a conservative silver-contact design within the stated rated load, consider **one external 2.2 kΩ pull-up to 3.3 V per button** (about 1.5 mA while pressed); verify supply/resistor tolerances and GPIO limits before adopting. This recommendation was subsequently adopted in the A0 carrier schematic; see the integration decision above. If low current is important, the datasheet also lists **B3F-1002-G** with gold contacts in the same p. 4 dimensional group, rated 100 µA–50 mA at 3–24 VDC, but with a different operating force (1.76 ±0.49 N); weak internal pull-ups are not automatically within that rated range either. It has not been selected or stock-checked here.
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The original A0 recommendation was 2.2 kΩ (about 1.5 mA); the purchased-part update uses **one external 2 kΩ 1% pull-up to 3.3 V per button** (nominal 1.65 mA while pressed); verify supply/resistor tolerances and GPIO limits before adopting. This recommendation was subsequently adopted in the A0 carrier schematic; see the integration decision above. If low current is important, the datasheet also lists **B3F-1002-G** with gold contacts in the same p. 4 dimensional group, rated 100 µA–50 mA at 3–24 VDC, but with a different operating force (1.76 ±0.49 N); weak internal pull-ups are not automatically within that rated range either. It has not been selected or stock-checked here.
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Retain firmware debouncing; a mechanical switch is not bounce-free. The device is unsealed (IP00), and the datasheet prohibits washing.
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@@ -1,5 +1,7 @@
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# DE-9 mechanical reference — pinned Adafruit 5988 STEP
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> **Current status (2026-09-22):** [User acceptance and group alignment](user-acceptance.md) supersedes the earlier pending user-fit, USB-clearance, male-map, procurement and mounting-hardware items below. Original research/evidence remains historical; acceptance is not independent qualification.
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Paths in prose point to the retained hardware artifacts or neighboring development notes.
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Commands keep their stated working directory; repository-root paths remain root-relative.
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@@ -1,5 +1,7 @@
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# Provisional carrier module footprints
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> **Current status (2026-09-22):** [User acceptance and group alignment](user-acceptance.md) supersedes the earlier pending user-fit, USB-clearance, male-map, procurement and mounting-hardware items below. Original research/evidence remains historical; acceptance is not independent qualification.
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Paths in prose point to the retained hardware artifacts or neighboring development notes.
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Commands keep their stated working directory; repository-root paths remain root-relative.
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@@ -1,5 +1,7 @@
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# Compact two-layer PCB — A1 draft
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> **Current status (2026-09-22):** [User acceptance and group alignment](user-acceptance.md) supersedes the earlier pending user-fit, USB-clearance, male-map, procurement and mounting-hardware items below. Original research/evidence remains historical; acceptance is not independent qualification.
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Paths in prose point to the retained hardware artifacts or neighboring development notes.
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Commands keep their stated working directory; repository-root paths remain root-relative.
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@@ -49,9 +51,9 @@ component body corners.
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|---|---|---|
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| U1 | (8, 23) | ESP32 left header pin 1; antenna toward top-left cutaway, USB toward bottom edge |
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| U2 | (43, 26.670) | MAX3243 header pin 1; bare module PCB front exactly flush with carrier top edge |
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| DS1 | (43, 36) | OLED module upper-left PCB corner; display faces up |
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| R1 / R2 / R3 | (43 / 54 / 65, 34) | Axial pull-ups in the gap between RS-232 and OLED |
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| SW1 / SW2 / SW3 | (43 / 55 / 67, 68) | Back, select, next below display; switch pad 1 origins |
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| DS1 | (43.970, 36) | OLED module upper-left PCB corner; display faces up |
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| R1 / R2 / R3 | (42.160 / 53.160 / 64.160, 32.6685) | Axial pull-ups in the gap between RS-232 and OLED |
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| SW1 / SW2 / SW3 | (41.720 / 53.720 / 65.720, 68) | Back, select, next below display; switch pad 1 origins |
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| H1 | (3.5, 22.5) | Proposed case mounting hole below antenna notch |
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| H2 | (3.5, 75) | Proposed case mounting hole near bottom-left edge |
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| H3 | (78, 4) | Proposed case mounting hole |
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@@ -61,12 +63,12 @@ Outline vertices: (36,0), (82,0), (82,80), (0,80), (0,19), (36,19), closed.
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The previous A0 board is retained in `../../../../hardware/PCB/validation/pcb-a0-before-reposition.kicad_pcb`.
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The board area is **58.76 cm²**; its bounding rectangle is 65.6 cm².
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H1–H4 are proposed **Ø3.2 mm NPTH M3 clearance holes**, not a previously agreed
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case specification. They are marked board-only and excluded from the electrical
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H1–H4 are user-approved **Ø3.2 mm NPTH M3 clearance holes**. The user selected
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10 mm brass standoffs into heat inserts; see the current acceptance record. They are marked board-only and excluded from the electrical
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BOM. The OLED and RS-232 module mounting holes are additional, separate holes.
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Screw heads, spacers, heat-set inserts, tool access and underside lead clearance
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must be checked against the final case and assembly heights. No insert dimensions
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or module stand-off heights are assumed.
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must be checked against the final case and assembly heights. Exact insert dimensions remain unspecified. The user intends/reports 10 mm
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assembled module elevation, not independently measured; see user-acceptance.md.
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## Routing and electrical status
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@@ -74,8 +76,8 @@ The PCB contains actual copper, not just ratsnest placement:
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- All **38 required physical-pad spanning connections** across **17 connected
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nets** routed, including both duplicated pads of each switch contact.
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- **565 segments**, signal width **0.25 mm**, 3.3 V and GND width **0.50 mm**.
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- **22 through vias**, **0.70 mm copper / 0.30 mm drill**.
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- **938 segments** after incremental group-alignment repair, signal width **0.25 mm**, 3.3 V and GND width **0.50 mm**.
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- **41 through vias** after repair, **0.70 mm copper / 0.30 mm drill**.
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- **No copper pours**; ground is explicitly routed. This is an initial routing
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solution, not a reviewed return-current/EMI or power-integrity design.
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- Proposed minimum different-net clearance **0.25 mm** and copper-edge clearance
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@@ -107,8 +109,7 @@ Missing RF clearance cannot be signed off from the current footprint alone.
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### RS-232
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U2 uses the new **`Carrier:MAX3243_Reference_Provisional`** footprint **on the PCB
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only**. Its bare-module outline/header/holes are adapted from published female
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U2 uses **`Carrier:MAX3243_Reference_Provisional`** in the schematic and PCB. Its bare-module outline/header/holes are adapted from published female
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5988 CAD for the intended male 6253 module. The user explicitly confirms identical
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male/female external dimensions. The linked Adafruit STEP has now been measured
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with OpenCascade; its nominal metal geometry is used on that basis. Male header
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@@ -143,12 +144,9 @@ the carrier edge. No wall thickness, cable-backshell clearance or sealing scheme
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has been assumed. The model's anchor legs extend **2.230 mm below the module
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underside**; select a stand-off/header stack or clearance solution before assembly.
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The schematic footprint remains intentionally blank, preserving its caution
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and avoiding edits to the schematic that was open in KiCad. Consequently there
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is **one known schematic-parity warning**: U2 footprint differs from the empty
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schematic assignment. This is not excluded/suppressed, and is not a net mismatch.
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Once the male footprint is qualified, explicitly assign it in the schematic
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before relying on Update PCB from Schematic to manage U2's footprint.
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The user has now confirmed male pinout/header/footprint equivalence and reviewed
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connections pin by pin. U2 is assigned in both schematic and PCB; validators
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require **zero schematic parity warnings**, without exclusions.
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### OLED and controls
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@@ -264,8 +262,8 @@ Run from the repository root with the system Python containing KiCad bindings:
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The first script exports a **fresh saved-schematic netlist** and checks the actual
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PCB pad assignments, component linkage, dimensions, layer count, nominal thickness,
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mounting holes, track/via sizes and KiCad DRC. It never rewrites the PCB or project.
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It reports the single expected U2 parity warning explicitly, and fails on any
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other parity issue, DRC violation or unconnected item. Reports are retained in
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It requires zero parity issues, DRC violations and unconnected items, including
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the retained user-confirmed U2 assignment. Reports are retained in
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`../../../../hardware/PCB/validation/pcb-parity-drc.json` and `../../../../hardware/PCB/validation/pcb-validation-summary.json`.
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The second independently checks continuous copper/hole/edge geometry and original
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@@ -291,7 +289,8 @@ Measurement-integration validation with KiCad **10.0.6**:
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- PCB, project and schematic retain their existing content except the authorized
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board graphics. No firmware/assets, reroute, upload, erase or hardware test.
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Current results:
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Historical measurement-integration results (current alignment results are in
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[user-acceptance.md](user-acceptance.md)):
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- **0 physical DRC errors/warnings; 0 unconnected items.**
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- All saved-schematic pad nets match the PCB; **1 expected U2 footprint parity warning**.
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@@ -1,5 +1,7 @@
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# MAX3243 carrier — PROVISIONAL female CAD reference / VERIFY MALE
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> **Current status (2026-09-22):** [User acceptance and group alignment](user-acceptance.md) supersedes the earlier pending user-fit, USB-clearance, male-map, procurement and mounting-hardware items below. Original research/evidence remains historical; acceptance is not independent qualification.
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Paths in prose point to the retained hardware artifacts or neighboring development notes.
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Commands keep their stated working directory; repository-root paths remain root-relative.
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@@ -0,0 +1,129 @@
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# Carrier group alignment and user acceptance — 2026-09-22
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This is the current acceptance record. It supersedes pending-user-confirmation
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items in the earlier research and A0/A1 notes; it does not replace their original
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manufacturer evidence or claim new hardware tests, fabrication approval or certification.
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## Saved placement
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Coordinates below are **carrier-local mm**, X right/Y down. Add (100,100) for
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KiCad coordinates. All footprint rotations remain zero. Body centres, not
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header/pad origins, define the common vertical axis **X=56.970 mm**.
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| Item | Old footprint origin | New footprint origin | Movement |
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| U2 RS-232 | (43,26.670) | unchanged | none |
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| DS1 OLED | (43,36) | (43.970,36) | +0.970 X |
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| R1 | (43,34) | (42.160,32.6685) | −0.840 X, −1.3315 Y |
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| R2 | (54,34) | (53.160,32.6685) | −0.840 X, −1.3315 Y |
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| R3 | (65,34) | (64.160,32.6685) | −0.840 X, −1.3315 Y |
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| SW1 | (43,68) | (41.720,68) | −1.280 X |
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| SW2 | (55,68) | (53.720,68) | −1.280 X |
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| SW3 | (67,68) | (65.720,68) | −1.280 X |
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U1 remains (8,23); carrier outline, four carrier mounting holes, RF reserve and
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confirmed USB geometry are unchanged. Resistors remain a horizontal group with
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11 mm pitch; buttons remain a horizontal group with 12 mm pitch. Neither group
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was rearranged into a vertical stack.
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The published RS-232 bare PCB spans X=41.095…72.845, Y=0…29.337, including
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its rounded rear corners beyond the header row. Its centre X=56.970 is retained
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to minimize module movement and preserve connector/case registration. OLED PCB
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bounds are X=43.970…69.970, Y=36…62. The OLED's offset display window is not
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used as the module centre.
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The nominal resistor bodies are 6.3 × 2.5 mm, centred 3.81 mm right of pad 1.
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Their group spans X=42.820…71.120, Y=31.4185…33.9185. The 6.663 mm gap between
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module boards is therefore split into **2.0815 mm clearance / 2.5 mm body /
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2.0815 mm clearance**. Adjacent resistor bodies have 4.7 mm horizontal clearance.
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These are nominal planar CAD clearances, not new tolerance or height measurements.
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Omron B3F-1000 nominal bodies are 6 × 6 mm with centres 3.25 mm right and
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2.25 mm below their pad-1 origins. Group body bounds X=41.970…71.970,
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Y=67.250…73.250; OLED-to-button body gap **5.250 mm**, adjacent button body
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gaps **6 mm**. Footprint courtyard and lead envelopes are wider than the bodies;
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the alignment audit uses the actual F.Fab bodies, not a pad-origin average.
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## Closed by explicit user acceptance/report
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- All component dimensions and physical fit match visually; USB placement and
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clearance are correct. This is user acceptance, not an independently performed
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new print-fit or hardware test by the agent.
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- Female headers are described as 8.5 mm and standard male headers as adding
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2.5 mm. User intends/reports **10 mm assembled elevation**. The arithmetic sum
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is 11 mm, but mating height cannot be inferred by simply adding those descriptions.
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**10 mm is not independently measured or precision-verified.** User reports
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RS-232 mounting prongs clear the carrier at the intended assembly height.
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- Four Ø3.2 mm M3 carrier holes approved; **10 mm brass standoffs into heat
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inserts**, M3 daughterboard screws, and **M2 display hardware** selected.
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This does not establish DE-9 cable-retention thread type, exact screw lengths,
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insert dimensions or the final printed case wall/cutout.
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- **Omron B3F-1000 switches purchased.** Existing standard KiCad footprint is
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retained; documented duplicate-pad mapping is unchanged.
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- **2 kΩ, 1% metal-film resistors purchased.** R1–R3 values updated in schematic,
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PCB and BOM; nominal DIN0207 6.3 × 2.5 mm body / 7.62 mm lead pitch retained
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under the visual-fit confirmation. Exact resistor MPN and purchased wattage
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were not supplied. Design requirement remains at least 0.125 W. At nominal
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3.3 V, each pressed external pull-up draws 1.65 mA and dissipates 5.445 mW;
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these calculations do not quantify regulator margin or GPIO internal pull-ups.
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- Male Adafruit module has identical reference pinout/header mapping/footprint
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per user, who reviewed module connections pin by pin. Existing schematic U2
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assignment `Carrier:MAX3243_Reference_Provisional` is preserved; clean parity
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is required, not waived. Original female CAD provenance is unchanged.
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- Nonisolated USB power arrangement explicitly accepted and reported already
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tested by user. **Successful operation does not establish backfeed safety**, in
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particular with simultaneous powered hosts. No isolation/backfeed protection
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was added or claimed.
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- Existing 3.3 V supply successfully powers the modules per user. This is operating
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evidence, not measured regulator current/thermal/transient headroom.
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- User confirms backside OLED I²C pull-ups and operation without extras. **Their
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resistance and termination rail remain unmeasured.** No values/rail are invented
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and no external I²C pull-ups added.
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- Current RF reserve and power/ground routing accepted based on visual and
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operational experience. This is not manufacturer RF qualification, measured
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signal/power integrity, regulator-margin proof, EMC testing or certification.
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## Verification and remaining limits
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Incremental routing starts from `hardware/PCB/validation/pcb-before-group-alignment.kicad_pcb`.
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It removes copper obstructed by moved pads, reconnects retained routes and trims
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KiCad-reported dangling stubs. **476/587 original copper items remain exactly
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unchanged**; 111 original items removed. No whole-board regeneration or route
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reset was used. `pcb-group-migration.json` records the removed UUIDs and repairs;
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`validate_group_alignment.py` checks the full parsed non-copper delta, retained
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copper UUID/content, body centrelines/gaps, and unchanged project settings.
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Original A0 and measured-U1 snapshots/reports are retained, not rebaselined.
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Run from repository root:
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```sh
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/usr/bin/python3 -B hardware/PCB/validate_schematic.py
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/usr/bin/python3 -B hardware/PCB/validate_pcb_draft.py
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/usr/bin/python3 -B hardware/PCB/validate_group_alignment.py
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/usr/bin/python3 -B hardware/PCB/validation/pcb-routing-check.py
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/usr/bin/python3 -B hardware/PCB/validate_u1_update.py
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/usr/bin/python3 -B hardware/PCB/validate_footprints.py
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/usr/bin/python3 -B hardware/PCB/reference/db9-cad/validate.py
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```
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Validation completed with KiCad 10.0.6: schematic ERC **0 errors/warnings**;
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PCB DRC **0 physical violations, 0 unconnected items, 0 parity issues**. All
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17 connected nets, 9 electrical components, 44 U1 pins and 15 firmware GPIO
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contracts checked. Current routing: **938 segments, 41 vias**; unchanged width
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rules (0.25 mm signal / 0.50 mm power and ground), 0.70/0.30 mm vias. Independent
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minimum different-net/copper-to-NPTH gap **0.252762 mm**, minimum board-edge gap
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**1.900 mm**; RF reserve remains clear. Exact group/preservation and U1/silk
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regressions, two footprint tests and DB9 CAD/source checks passed. KiCad bindings
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emit known startup enum-property assertions but all checks complete successfully.
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DB9 projections and 94 device-silkscreen items refreshed. Placement PDF (1:1),
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PCB SVG/PNG/3D and schematic PDF/SVG/PNG regenerated; PNG previews visually
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reviewed. The 3D view still lacks complete module models and is not assembly
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qualification. No removed PCB presentation/draft markers were reintroduced.
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Current acceptance closes the user-review gates above. Still not independently
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qualified: regulator margin, USB backfeed safety, pull-up values/rail, RF/EMC,
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complete tolerance/height/case/actuator envelopes, finished-hole fabrication
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process and certification. Missing module courtyards remain a known model limit;
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DRC does not validate complete assembled-module or case fit. No new hardware
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tests, firmware changes, Gerbers, fabrication order or manufacturing approval.
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Block a user