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Record Accepted PCB Placement And Fit

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Align component groups, repair affected routing, and add preservation
audits.
Assign the confirmed U2 footprint and update pull-ups to 2 kΩ across
design files.
Document user acceptance, switch to an A3 worksheet, and refresh PCB
exports.
This commit is contained in:
Commander1024
2026-09-22 10:28:08 +02:00
parent 901afbe754
commit c257158ada
42 changed files with 29500 additions and 17205 deletions
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docs/devel/hardware/PCB/pcb-draft-notes.md
+19 -20
View File
@@ -1,5 +1,7 @@
# Compact two-layer PCB — A1 draft
> **Current status (2026-09-22):** [User acceptance and group alignment](user-acceptance.md) supersedes the earlier pending user-fit, USB-clearance, male-map, procurement and mounting-hardware items below. Original research/evidence remains historical; acceptance is not independent qualification.
Paths in prose point to the retained hardware artifacts or neighboring development notes.
Commands keep their stated working directory; repository-root paths remain root-relative.
@@ -49,9 +51,9 @@ component body corners.
|---|---|---|
| U1 | (8, 23) | ESP32 left header pin 1; antenna toward top-left cutaway, USB toward bottom edge |
| U2 | (43, 26.670) | MAX3243 header pin 1; bare module PCB front exactly flush with carrier top edge |
| DS1 | (43, 36) | OLED module upper-left PCB corner; display faces up |
| R1 / R2 / R3 | (43 / 54 / 65, 34) | Axial pull-ups in the gap between RS-232 and OLED |
| SW1 / SW2 / SW3 | (43 / 55 / 67, 68) | Back, select, next below display; switch pad 1 origins |
| DS1 | (43.970, 36) | OLED module upper-left PCB corner; display faces up |
| R1 / R2 / R3 | (42.160 / 53.160 / 64.160, 32.6685) | Axial pull-ups in the gap between RS-232 and OLED |
| SW1 / SW2 / SW3 | (41.720 / 53.720 / 65.720, 68) | Back, select, next below display; switch pad 1 origins |
| H1 | (3.5, 22.5) | Proposed case mounting hole below antenna notch |
| H2 | (3.5, 75) | Proposed case mounting hole near bottom-left edge |
| H3 | (78, 4) | Proposed case mounting hole |
@@ -61,12 +63,12 @@ Outline vertices: (36,0), (82,0), (82,80), (0,80), (0,19), (36,19), closed.
The previous A0 board is retained in `../../../../hardware/PCB/validation/pcb-a0-before-reposition.kicad_pcb`.
The board area is **58.76 cm²**; its bounding rectangle is 65.6 cm².
H1–H4 are proposed **Ø3.2 mm NPTH M3 clearance holes**, not a previously agreed
case specification. They are marked board-only and excluded from the electrical
H1–H4 are user-approved **Ø3.2 mm NPTH M3 clearance holes**. The user selected
10 mm brass standoffs into heat inserts; see the current acceptance record. They are marked board-only and excluded from the electrical
BOM. The OLED and RS-232 module mounting holes are additional, separate holes.
Screw heads, spacers, heat-set inserts, tool access and underside lead clearance
must be checked against the final case and assembly heights. No insert dimensions
or module stand-off heights are assumed.
must be checked against the final case and assembly heights. Exact insert dimensions remain unspecified. The user intends/reports 10 mm
assembled module elevation, not independently measured; see user-acceptance.md.
## Routing and electrical status
@@ -74,8 +76,8 @@ The PCB contains actual copper, not just ratsnest placement:
- All **38 required physical-pad spanning connections** across **17 connected
nets** routed, including both duplicated pads of each switch contact.
- **565 segments**, signal width **0.25 mm**, 3.3 V and GND width **0.50 mm**.
- **22 through vias**, **0.70 mm copper / 0.30 mm drill**.
- **938 segments** after incremental group-alignment repair, signal width **0.25 mm**, 3.3 V and GND width **0.50 mm**.
- **41 through vias** after repair, **0.70 mm copper / 0.30 mm drill**.
- **No copper pours**; ground is explicitly routed. This is an initial routing
solution, not a reviewed return-current/EMI or power-integrity design.
- Proposed minimum different-net clearance **0.25 mm** and copper-edge clearance
@@ -107,8 +109,7 @@ Missing RF clearance cannot be signed off from the current footprint alone.
### RS-232
U2 uses the new **`Carrier:MAX3243_Reference_Provisional`** footprint **on the PCB
only**. Its bare-module outline/header/holes are adapted from published female
U2 uses **`Carrier:MAX3243_Reference_Provisional`** in the schematic and PCB. Its bare-module outline/header/holes are adapted from published female
5988 CAD for the intended male 6253 module. The user explicitly confirms identical
male/female external dimensions. The linked Adafruit STEP has now been measured
with OpenCascade; its nominal metal geometry is used on that basis. Male header
@@ -143,12 +144,9 @@ the carrier edge. No wall thickness, cable-backshell clearance or sealing scheme
has been assumed. The model's anchor legs extend **2.230 mm below the module
underside**; select a stand-off/header stack or clearance solution before assembly.
The schematic footprint remains intentionally blank, preserving its caution
and avoiding edits to the schematic that was open in KiCad. Consequently there
is **one known schematic-parity warning**: U2 footprint differs from the empty
schematic assignment. This is not excluded/suppressed, and is not a net mismatch.
Once the male footprint is qualified, explicitly assign it in the schematic
before relying on Update PCB from Schematic to manage U2's footprint.
The user has now confirmed male pinout/header/footprint equivalence and reviewed
connections pin by pin. U2 is assigned in both schematic and PCB; validators
require **zero schematic parity warnings**, without exclusions.
### OLED and controls
@@ -264,8 +262,8 @@ Run from the repository root with the system Python containing KiCad bindings:
The first script exports a **fresh saved-schematic netlist** and checks the actual
PCB pad assignments, component linkage, dimensions, layer count, nominal thickness,
mounting holes, track/via sizes and KiCad DRC. It never rewrites the PCB or project.
It reports the single expected U2 parity warning explicitly, and fails on any
other parity issue, DRC violation or unconnected item. Reports are retained in
It requires zero parity issues, DRC violations and unconnected items, including
the retained user-confirmed U2 assignment. Reports are retained in
`../../../../hardware/PCB/validation/pcb-parity-drc.json` and `../../../../hardware/PCB/validation/pcb-validation-summary.json`.
The second independently checks continuous copper/hole/edge geometry and original
@@ -291,7 +289,8 @@ Measurement-integration validation with KiCad **10.0.6**:
- PCB, project and schematic retain their existing content except the authorized
board graphics. No firmware/assets, reroute, upload, erase or hardware test.
Current results:
Historical measurement-integration results (current alignment results are in
[user-acceptance.md](user-acceptance.md)):
- **0 physical DRC errors/warnings; 0 unconnected items.**
- All saved-schematic pad nets match the PCB; **1 expected U2 footprint parity warning**.