Record Accepted PCB Placement And Fit
Align component groups, repair affected routing, and add preservation audits. Assign the confirmed U2 footprint and update pull-ups to 2 kΩ across design files. Document user acceptance, switch to an A3 worksheet, and refresh PCB exports.
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# Carrier group alignment and user acceptance — 2026-09-22
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This is the current acceptance record. It supersedes pending-user-confirmation
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items in the earlier research and A0/A1 notes; it does not replace their original
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manufacturer evidence or claim new hardware tests, fabrication approval or certification.
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## Saved placement
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Coordinates below are **carrier-local mm**, X right/Y down. Add (100,100) for
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KiCad coordinates. All footprint rotations remain zero. Body centres, not
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header/pad origins, define the common vertical axis **X=56.970 mm**.
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| Item | Old footprint origin | New footprint origin | Movement |
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|---|---|---|---|
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| U2 RS-232 | (43,26.670) | unchanged | none |
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| DS1 OLED | (43,36) | (43.970,36) | +0.970 X |
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| R1 | (43,34) | (42.160,32.6685) | −0.840 X, −1.3315 Y |
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| R2 | (54,34) | (53.160,32.6685) | −0.840 X, −1.3315 Y |
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| R3 | (65,34) | (64.160,32.6685) | −0.840 X, −1.3315 Y |
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| SW1 | (43,68) | (41.720,68) | −1.280 X |
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| SW2 | (55,68) | (53.720,68) | −1.280 X |
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| SW3 | (67,68) | (65.720,68) | −1.280 X |
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U1 remains (8,23); carrier outline, four carrier mounting holes, RF reserve and
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confirmed USB geometry are unchanged. Resistors remain a horizontal group with
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11 mm pitch; buttons remain a horizontal group with 12 mm pitch. Neither group
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was rearranged into a vertical stack.
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The published RS-232 bare PCB spans X=41.095…72.845, Y=0…29.337, including
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its rounded rear corners beyond the header row. Its centre X=56.970 is retained
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to minimize module movement and preserve connector/case registration. OLED PCB
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bounds are X=43.970…69.970, Y=36…62. The OLED's offset display window is not
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used as the module centre.
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The nominal resistor bodies are 6.3 × 2.5 mm, centred 3.81 mm right of pad 1.
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Their group spans X=42.820…71.120, Y=31.4185…33.9185. The 6.663 mm gap between
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module boards is therefore split into **2.0815 mm clearance / 2.5 mm body /
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2.0815 mm clearance**. Adjacent resistor bodies have 4.7 mm horizontal clearance.
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These are nominal planar CAD clearances, not new tolerance or height measurements.
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Omron B3F-1000 nominal bodies are 6 × 6 mm with centres 3.25 mm right and
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2.25 mm below their pad-1 origins. Group body bounds X=41.970…71.970,
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Y=67.250…73.250; OLED-to-button body gap **5.250 mm**, adjacent button body
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gaps **6 mm**. Footprint courtyard and lead envelopes are wider than the bodies;
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the alignment audit uses the actual F.Fab bodies, not a pad-origin average.
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## Closed by explicit user acceptance/report
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- All component dimensions and physical fit match visually; USB placement and
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clearance are correct. This is user acceptance, not an independently performed
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new print-fit or hardware test by the agent.
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- Female headers are described as 8.5 mm and standard male headers as adding
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2.5 mm. User intends/reports **10 mm assembled elevation**. The arithmetic sum
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is 11 mm, but mating height cannot be inferred by simply adding those descriptions.
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**10 mm is not independently measured or precision-verified.** User reports
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RS-232 mounting prongs clear the carrier at the intended assembly height.
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- Four Ø3.2 mm M3 carrier holes approved; **10 mm brass standoffs into heat
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inserts**, M3 daughterboard screws, and **M2 display hardware** selected.
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This does not establish DE-9 cable-retention thread type, exact screw lengths,
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insert dimensions or the final printed case wall/cutout.
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- **Omron B3F-1000 switches purchased.** Existing standard KiCad footprint is
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retained; documented duplicate-pad mapping is unchanged.
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- **2 kΩ, 1% metal-film resistors purchased.** R1–R3 values updated in schematic,
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PCB and BOM; nominal DIN0207 6.3 × 2.5 mm body / 7.62 mm lead pitch retained
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under the visual-fit confirmation. Exact resistor MPN and purchased wattage
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were not supplied. Design requirement remains at least 0.125 W. At nominal
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3.3 V, each pressed external pull-up draws 1.65 mA and dissipates 5.445 mW;
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these calculations do not quantify regulator margin or GPIO internal pull-ups.
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- Male Adafruit module has identical reference pinout/header mapping/footprint
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per user, who reviewed module connections pin by pin. Existing schematic U2
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assignment `Carrier:MAX3243_Reference_Provisional` is preserved; clean parity
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is required, not waived. Original female CAD provenance is unchanged.
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- Nonisolated USB power arrangement explicitly accepted and reported already
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tested by user. **Successful operation does not establish backfeed safety**, in
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particular with simultaneous powered hosts. No isolation/backfeed protection
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was added or claimed.
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- Existing 3.3 V supply successfully powers the modules per user. This is operating
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evidence, not measured regulator current/thermal/transient headroom.
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- User confirms backside OLED I²C pull-ups and operation without extras. **Their
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resistance and termination rail remain unmeasured.** No values/rail are invented
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and no external I²C pull-ups added.
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- Current RF reserve and power/ground routing accepted based on visual and
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operational experience. This is not manufacturer RF qualification, measured
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signal/power integrity, regulator-margin proof, EMC testing or certification.
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## Verification and remaining limits
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Incremental routing starts from `hardware/PCB/validation/pcb-before-group-alignment.kicad_pcb`.
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It removes copper obstructed by moved pads, reconnects retained routes and trims
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KiCad-reported dangling stubs. **476/587 original copper items remain exactly
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unchanged**; 111 original items removed. No whole-board regeneration or route
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reset was used. `pcb-group-migration.json` records the removed UUIDs and repairs;
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`validate_group_alignment.py` checks the full parsed non-copper delta, retained
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copper UUID/content, body centrelines/gaps, and unchanged project settings.
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Original A0 and measured-U1 snapshots/reports are retained, not rebaselined.
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Run from repository root:
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```sh
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/usr/bin/python3 -B hardware/PCB/validate_schematic.py
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/usr/bin/python3 -B hardware/PCB/validate_pcb_draft.py
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/usr/bin/python3 -B hardware/PCB/validate_group_alignment.py
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/usr/bin/python3 -B hardware/PCB/validation/pcb-routing-check.py
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/usr/bin/python3 -B hardware/PCB/validate_u1_update.py
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/usr/bin/python3 -B hardware/PCB/validate_footprints.py
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/usr/bin/python3 -B hardware/PCB/reference/db9-cad/validate.py
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```
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Validation completed with KiCad 10.0.6: schematic ERC **0 errors/warnings**;
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PCB DRC **0 physical violations, 0 unconnected items, 0 parity issues**. All
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17 connected nets, 9 electrical components, 44 U1 pins and 15 firmware GPIO
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contracts checked. Current routing: **938 segments, 41 vias**; unchanged width
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rules (0.25 mm signal / 0.50 mm power and ground), 0.70/0.30 mm vias. Independent
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minimum different-net/copper-to-NPTH gap **0.252762 mm**, minimum board-edge gap
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**1.900 mm**; RF reserve remains clear. Exact group/preservation and U1/silk
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regressions, two footprint tests and DB9 CAD/source checks passed. KiCad bindings
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emit known startup enum-property assertions but all checks complete successfully.
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DB9 projections and 94 device-silkscreen items refreshed. Placement PDF (1:1),
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PCB SVG/PNG/3D and schematic PDF/SVG/PNG regenerated; PNG previews visually
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reviewed. The 3D view still lacks complete module models and is not assembly
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qualification. No removed PCB presentation/draft markers were reintroduced.
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Current acceptance closes the user-review gates above. Still not independently
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qualified: regulator margin, USB backfeed safety, pull-up values/rail, RF/EMC,
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complete tolerance/height/case/actuator envelopes, finished-hole fabrication
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process and certification. Missing module courtyards remain a known model limit;
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DRC does not validate complete assembled-module or case fit. No new hardware
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tests, firmware changes, Gerbers, fabrication order or manufacturing approval.
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