Record Accepted PCB Placement And Fit

Align component groups, repair affected routing, and add preservation
audits.
Assign the confirmed U2 footprint and update pull-ups to 2 kΩ across
design files.
Document user acceptance, switch to an A3 worksheet, and refresh PCB
exports.

hardware/PCB/validate_u1_update.py

@@ -59,7 +59,11 @@ def main():
     u1_ids = {str(uuid.uuid5(U1_NS,str(i))) for i in range(6)}
     # The original baseline retains historical draft labels. Permit only the
     # exact requested title/revision/comment edits and removal of the silk label.
-    assert canonical(expected_tree(parse(BASE)), silk_ids) == canonical(parse(PCB), silk_ids | u1_ids), "Change outside owned U1 additions / device silk / exact presentation labels"
+    # Keep proving the original integration against its original evidence, then
+    # audit the explicitly authorized subsequent placement/routing delta.
+    from validate_group_alignment import audit, BASE as GROUP_BASE
+    assert canonical(expected_tree(parse(BASE)), silk_ids) == canonical(parse(GROUP_BASE), silk_ids | u1_ids), "Historical U1 integration changed"
+    audit()
     generated = [g for g in board.GetDrawings() if g.m_Uuid.AsString() in silk_ids]
     assert not any(isinstance(g,p.PCB_TEXT) and g.GetText()=="HEADER GUIDES" for g in board.GetDrawings())
     carrier = Polygon([(136,100),(182,100),(182,180),(100,180),(100,119),(136,119)])
@@ -92,7 +96,7 @@ def main():
     assert PCB.read_bytes() == before
     assert not (ROOT/"~serial-carrier.kicad_pcb.lck").exists()
     summary = dict(measured_library_matches_embedded_u1=True,
-                   existing_uuids_pads_nets_placement_routing_settings_and_unrelated_graphics_preserved=True,
+                   historical_u1_integration_and_subsequent_authorized_group_delta_verified=True,
                    presentation_label_cleanup=True,
                    silk_refresh_idempotent=True, stale_geometry_negative_control=True,
                    silk_clipped_to_carrier=True, usb_mouth_markers=2,
@@ -100,7 +104,7 @@ def main():
                    baseline_sha256=hashlib.sha256(BASE.read_bytes()).hexdigest(),
                    board_sha256=hashlib.sha256(before).hexdigest(),
                    project_sha256=hashlib.sha256((ROOT/"serial-carrier.kicad_pro").read_bytes()).hexdigest())
-    (ROOT/"validation/pcb-u1-update.json").write_text(json.dumps(summary,indent=2)+"\n")
+    (ROOT/"validation/pcb-u1-group-regression.json").write_text(json.dumps(summary,indent=2)+"\n")
     print(json.dumps(summary,indent=2))