Commander1024/ESP32_Serial_Swiss_Army_Knife
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Integrate DB9 mounting into enclosure lid

Browse Source
This commit is contained in:
Commander1024
2026-09-26 13:50:55 +02:00
parent f925293d3f
commit c5bf3e32f5
12 changed files with 7349 additions and 15164 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hardware/case/checks.md
+59 -26
View File
@@ -1,46 +1,79 @@
# Corrected enclosure checks — 2026-09-26
# Integral-cover connector mounting checks — 2026-09-26
This supersedes the initial under-carrier-brass stack. It is a CAD validation record, **not physical acceptance**. Tools already installed: OpenSCAD 2021.01, system Python 3 and KiCad `pcbnew`. No packages downloaded/installed. PCB hardware files were read only.
This supersedes the separate DB9 panel/insert-hanger design. **CAD evidence, not physical acceptance.** Installed OpenSCAD 2021.01 and system Python/KiCad were used without downloads. PCB files were read only; changes are confined to the case and agent current-state record.
## Default design
## Geometry and outputs
Commands are in [README.md](README.md). All four printable part exports completed within bounded 180-second command timeouts, with OpenSCAD CGAL reporting `Simple: yes`:
Shell remains **106 × 86.8 × 37.4 mm**; carrier underside/top **Z7.4/9**, brass bodies 10 mm above carrier, module underside **Z19**, roof underside **Z35**. RF overlay remains removed; PCB layout/copper/reserve unchanged.
| Export | Connected triangle components | Triangle count |
- Integral panel: nominal X33…81 (0.02 mm union overlap into each wall), Y−0.47…1.93, Z21.07…35, **2.4 mm clamp thickness**. Direct roof connection, two **6 mm nominal** forward ribs (inner edges unchanged) outside the flange; no DB9 heat inserts or independent attachment screws.
- Closed **Ø3.6** post-clearance holes, **25 mm** spacing, axis Z26.84762024. No M3/4-40 inference.
- Bottom-open **18.078038 mm** shell slot; top Z31.99762024. Minimum hole-to-slot web **1.660981 mm**; top rail **3.00238 mm**. Panel bottom clears module PCB by 0.5 mm; anchors begin 3.10 mm behind the panel rear. Flange registration comes from extracted STEP faces, not the module mounting-hole pitch.
- Former 1 mm side slits closed by panel/rib extensions into wall boundaries. Base shoulders: X33.25…80.75, top Z20.82; central tongue width 17.578038, top Z21.69762024 (0.6 below STEP shell). Upstand Y−3.4…−0.5, depth 2.9: PCB-edge clearance 0.5, anchor separation 5.53. Shoulder/edge/tongue seams 0.25. No undercut, no change to 36 mm cable approach width.
- Front-wall service recess extends down to lid seam. USB opening stays unchanged; installation is vertical with all cables and both connector posts removed, not a horizontal slide under button guides.
- Deleted `panel-default.stl`, panel mode and layout object. `db_panel=false` is access-only. Base insert count is **10 M3 + 4 M2**.
Affected base/lid exports regenerated; unchanged plungers retained and revalidated under bounded 180-second command timeouts; CGAL reported `Simple: yes`:
| Export | Connected triangle components | Triangles |
|---|---:|---:|
| `base-default.stl` | 1 | 8364 |
| `lid-default.stl` | 1 | 13080 |
| `panel-default.stl` | 1 | 816 |
| `base-default.stl` | 1 | 8404 |
| `lid-default.stl` | 1 | 12712 |
| `plungers-default.stl` | 3 | 1716 |
The shell is **106 × 86.8 × 37.4 mm** (roof), 10 mm lower than the initial mistaken stack. Carrier underside/top are **Z7.4/9**, module underside **Z19**, roof underside **Z35**. The base top descends to Z15. The lid, panel, plungers, USB bay, DB9 hangers and display all descend with their parent datums; their relative fit remains unchanged. Print-local lid/panel/plunger nominal dimensions therefore remain unchanged, although all exports were regenerated. Gold hardware references replace printed spacers; no under-carrier brass, printable spacer mode, layout spacers or active spacer STL remains. The obsolete initial spacer STL had no unstaged user modifications before removal.
Base and lid geometry changed only at the connector closure; plunger geometry is unchanged. The lid is one connected printable part, not overlapping separate exports. Three PNGs (`assembly-preview.png`, `db9-preview.png`, `lid-detail.png`) regenerated headlessly under 120-second timeouts and visually reviewed. The bare-lid view exposes the closed post holes, open-bottom shell slot, forward ribs and downward guides; the assembled view shows reseated post-body references outside the panel. Simplified background references are not production component CAD.
`/usr/bin/python3 validate.py --source` passed:
## Source, expressions and mesh regression
- Actual SCAD-evaluated default stack, including roof, split, button/guide, DB9 axis/panel bottom, USB bay and plunger length.
- Independent `carrier_boss_h=7` fixture moves assembly Z by 2 without changing plunger length; `module_gap=12, lid_above_carrier=28` raises modules/roof/ports and lengthens plungers without moving the carrier or button contact.
- Reference 4 mm studs cross the 1.6 mm carrier and give 2.4 mm nominal engagement. Negative fixtures reject an M3 stud that cannot reach past the carrier, an M2 stud that bottoms in the pocket, and a 0.8 mm shell wall.
- Analytical 0.4 mm nozzle checks: shell/floor/roof at least three nozzle widths; insert entry and guide webs at least two. The limiting default panel-hanger entry web is 0.8 mm, M3 daughter entry web 1.1 mm, M2 daughter entry web 1.1 mm and guide radial web 1.75 mm. These selected web checks are not slicer coverage or proof that all text/features print reliably.
- Native PCB outline vertex set, 1.6 mm thickness, U1/U2/DS1 registration and orientation.
- Actual carrier/daughterboard NPTH centres **and diameters** (carrier 3.2, RS-232 3, OLED 2), no U1 NPTH mounting holes, and button body centres. The ESP32 remains header-supported; no mounting holes were invented.
- Saved measured U1 USB mouth graphic centres/widths and mouth Y; extracted STEP shell bounds and front-lock axes (25 mm, not 24.13 mm module holes).
- Every exported triangle has nonzero area, every edge has exactly two oppositely wound uses, positive total signed volume, expected connected component counts, bottom Z≈0 and default maximum bounds (including the shortened base) to detect stale exports. These are **edge-manifold checks**, not an exhaustive mesh-intersection/vertex-manifold proof.
Run from this directory:
KiCad emitted its known enum-property assertions but completed. It did not save or regenerate the board.
```sh
/usr/bin/python3 -B validate.py --source --installation --variants
```
PNG rendering succeeded headlessly with `QT_QPA_PLATFORM=offscreen`, within a bounded 120-second command timeout. Both `assembly-preview.png` and `db9-preview.png` were visually inspected: lower base, gold supports above carrier, simplified ESP32 header supports, separated lid/base, button tips, raised labels, USB bay and externally approachable DB9 panel. No red RF overlay remains. The actual projecting antenna rectangle is retained; the enclosure no longer reserves the PCB RF region. PCB copper/reserve/layout/schematic are unchanged and no Wi-Fi performance guarantee is implied. Hardware envelopes are incomplete; stock connector-post references still intentionally overlap the panel to expose the required replacement/reseating. Visual review does not certify clearance.
PASS:
- Native saved PCB outline, thickness, placements/orientations, carrier/module NPTH centres **and diameters**, no invented ESP32 mounting holes, button centres and measured USB mouth graphics.
- Extracted STEP flange plane/lateral bounds, shell size and true 25 mm lock axes. Read-only KiCad emitted its known enum-property assertions but completed.
- Actual SCAD-evaluated stack/connector expressions; independent raised-carrier and taller-module fixtures; stud engagement; obsolete panel/spacer rejection.
- Negative assertions for insufficient stud reach, bottoming studs, thin shell/panel, negative flange gap, panel entering the PCB plane, oversized lock holes consuming slot ligaments, ribs entering flange lateral bounds, insufficient sliding seam/shell clearance and inverted closure steps.
- Every STL triangle nondegenerate, every edge used twice with opposite winding, expected component counts, positive total volume, print-bed Z and expected bounds. These are **edge-manifold checks**, not exhaustive vertex-manifold or self-intersection proof.
## Continuous installation sweep
`--installation` renders CGAL intersections of the **actual lid** with rectangular hardware envelopes swept continuously through **60 mm of relative vertical travel**, from below to the final position. A remote 1 mm³ sentinel makes an empty intersection exportable; a passing result has only that cube, one component and exactly 1 mm³ volume.
Included envelopes: maximum shell root/lip, flange, STEP anchor-bracket bounds, RS-232/ESP32/OLED boards, antenna, provisional OLED glass and USB shells, full button-body/actuator bounding boxes and conservative square base-boss bounds. Flange contact is inset 0.01 mm solely to avoid a coincident CGAL face; physical tolerances are not inferred. No cable envelopes are included because **cables must be disconnected**. Plungers move with the lid and contact the switches at final seating; their return/retention remains an independent physical gate.
- **PASS default**: posts removed, zero modeled swept interference.
- **PASS variant**: `carrier_boss_h=7`, `module_gap=12`, `lid_above_carrier=28`, `panel_t=3`.
- **PASS clearance variant**: `seam_clearance=0.4`, `shell_margin=0.8`, `end_clearance=1.5`.
- Each test also intersects the actual base/lid at seating, sweeps both upstand steps separately downward 60 mm against the lid, and sweeps electronics envelopes upward 60 mm against the new base material (equivalent to vertical electronics insertion). Only the sentinel remains. Existing conservative base-boss envelopes remain included.
- An initial full-base Minkowski sweep exceeded the outer 240-second command timeout after default passed. Replacing it with a whole-upstand hull introduced false diagonal interference; the final per-step exact sweep avoids that invented material and completes within the bounded runs.
- **PASS negative control**: restoring original post-body envelopes causes detected interference, demonstrating that leaving posts installed is not an allowed assembly path.
The first thicker-panel sweep exposed a thin residual inner-wall strip where the panel front lay forward of the original wall's inner face. The recess now clears at least the full wall thickness, independently of panel depth; the corrected fixture passes. The recess starts at the lid seam; the new forward-only base upstand occupies its lower portion.
These are selected conservative nominal envelopes, not a full STEP solid-motion/real-component qualification. Unknown socket bodies, component details, wires, tolerances and actual USB/glass heights remain outside the proof.
## Parameter CGAL smoke tests
Temporary STL files were rendered and checked for one closed consistently wound edge-manifold component:
Rendered to temporary files (180-second limit per render), then checked with `validate.mesh_check(path, 1)` for a single closed, consistently wound edge-manifold component:
```sh
QT_QPA_PLATFORM=offscreen openscad -o /tmp/case-correction-variant-lid.stl -D 'part="lid"' -D 'module_gap=12' -D 'lid_above_carrier=28' -D 'carrier_boss_h=7' -D 'emboss=false' -D 'db_panel=false' enclosure.scad
QT_QPA_PLATFORM=offscreen openscad -o /tmp/case-correction-variant-base.stl -D 'part="base"' -D 'daughter_supports=false' -D 'side_extra=14' -D 'm3_insert_d=4.4' -D 'panel_mount_boss_d=7' enclosure.scad
QT_QPA_PLATFORM=offscreen openscad -o /tmp/case-integral-variant-lid.stl -D 'part="lid"' -D 'carrier_boss_h=7' -D 'module_gap=12' -D 'lid_above_carrier=28' -D 'panel_t=3' -D 'emboss=false' enclosure.scad
QT_QPA_PLATFORM=offscreen openscad -o /tmp/case-integral-access-lid.stl -D 'part="lid"' -D 'db_panel=false' -D 'emboss=false' enclosure.scad
QT_QPA_PLATFORM=offscreen openscad -o /tmp/case-integral-variant-base.stl -D 'part="base"' -D 'daughter_supports=false' -D 'side_extra=14' -D 'm3_insert_d=4.4' enclosure.scad
```
Both reported `Simple: yes`. The first is a 41.4 mm roof-height configuration, lid export 3848 triangles. The second is a 110 mm-wide base, 4972 triangles. These test parameter propagation; **neither alternative is a selected or physically validated stack**. Arbitrary parameter combinations are not guaranteed valid; review every regenerated assembly.
The repeatable `--variants` suite now covers these three configurations plus a raised/thicker-panel **base**. All four PASS CGAL and one-component edge-manifold checks. These exercise a thicker integral panel with raised stack, access-only lid and wider base/alternate insert pocket. They are not selected or physically validated configurations. Arbitrary parameter combinations are not guaranteed valid. `git diff --check` also passed.
## Explicit limits
## Hardware gates — unresolved, not hidden by CAD success
No physical print, slicer analysis, insert installation, board assembly, connector/thread fit, plunger return/overload test, cable-load test, RF/thermal check or firmware test was performed. No full solid-interference solver was used. In particular, 5 mm carrier-to-floor clearance must be checked against actual solder/prongs, and conductive brass shoulders/insert faces against real lands/traces. Stud lengths, upper female depths, insert usable threads, USB Z/overmoulds, display height and DB9 hardware are still provisional as detailed in the README. The DB9 retention concept remains conditional on verified compatible panel jackscrews; stock posts are not claimed to fit the panel.
1. Verify posts really unscrew and determine **actual thread/pitch**, under-shoulder stud length, female depth, required engagement, clamp torque and compatibility with any captive connector hardware. No thread is established by the STEP bore.
2. Default panel consumes **2.4 mm additional reach**: engagement = stud length − 2.4 − washers (− any flange gap). Stock studs may be too short. Verified longer-stud posts/extensions may be needed; do not bottom them or use ordinary screws in the cable-lock mouths.
3. A same-length 4.8 mm body reseated outside the panel moves its mouth from Y−2.870 to **Y−5.270**, now **1.4 mm ahead of the shell nose**. Full mating may fail despite adequate thread engagement. A compatible shorter-body/panel-mount solution must be measured; a nominal 2.4 mm body would restore the old mouth plane but is **not a qualified available part or sufficient female-thread-depth claim**.
4. Preserve full cable mating/locking and external nose protrusion (0.47 mm beyond ordinary wall, 3.4 mm beyond panel); verify actual hood and wrench access inside the **36 mm** central space between ribs. Revise geometry/hardware if necessary rather than forcing a fit.
5. Existing gates remain: insert selection, underside solder/prong and conductive shoulder clearances, header/brass stack agreement, USB envelopes, glass height, button preload/return/overload, material/print orientation and cable-load strength.
No physical print, slicer analysis, insert installation, connector/thread measurement, full cable mating, load, RF, thermal, firmware or device test was performed. The stronger integral load path is designed and modeled, **not mechanically load-qualified**.