Add Network Tools And Nested Command Completion

wiring.md

@@ -126,13 +126,13 @@ DE-9 pin 4 DTR  ─────> pin 6 DSR
 DE-9 pin 7 RTS  ─────> pin 8 CTS
 ```
 
-Run `loopback-a`. The firmware cycles all eight TX/DTR/RTS logic combinations, waits for the MAX3243 outputs and receivers to settle, and verifies all three receiver states plus `VLD`. Two inversions occur—once in the driver and once in the receiver—so the final ESP32 logic levels must match.
+Run `debug loopback-a`. The firmware cycles all eight TX/DTR/RTS logic combinations, waits for the MAX3243 outputs and receivers to settle, and verifies all three receiver states plus `VLD`. Two inversions occur—once in the driver and once in the receiver—so the final ESP32 logic levels must match.
 
 Configuration A can also be used for:
 
-- `valid-test`, with no external RS-232 peer connected.
-- `uart-loopback <baud> [format] [bytes]`, although only the pin 3 to pin 2 link is needed by that command.
-- `uart-suite`, again using only the pin 3 to pin 2 data link.
+- `debug valid-test`, with no external RS-232 peer connected.
+- `debug uart-loopback <baud> [format] [bytes]`, although only the pin 3 to pin 2 link is needed by that command.
+- `debug uart-suite`, again using only the pin 3 to pin 2 data link.
 
 ### Configuration B: remaining receivers
 
@@ -150,7 +150,7 @@ DE-9 pin 4 DTR  ─────> pin 9 RI
 DE-9 pin 7 RTS  ─────> pin 2 RX
 ```
 
-Run `loopback-b`. Together, configurations A and B exercise all three MAX3243 drivers and all five receivers.
+Run `debug loopback-b`. Together, configurations A and B exercise all three MAX3243 drivers and all five receivers.
 
 ### Configuration C: CTS transmit gating
 
@@ -166,7 +166,7 @@ DE-9 pin 3 TX   ─────> pin 2 RX
 DE-9 pin 4 DTR  ─────> pin 8 CTS
 ```
 
-Run `cts-flow-test`. The test operates UART1 at 115200 baud with hardware CTS enabled and performs two phases:
+Run `debug cts-flow-test`. The test operates UART1 at 115200 baud with hardware CTS enabled and performs two phases:
 
 1. DTR logic 1 produces CTS logic 1, the inactive/high state. The firmware queues 512 bytes and verifies that transmission does not complete and no byte reaches RX during a 250 ms observation period.
 2. DTR changes to logic 0, producing active/low CTS. The queued transmission must resume automatically, and all 512 bytes must return through RX without missing, extra, or corrupted data and without UART errors.
@@ -187,7 +187,7 @@ UART2 TX / DE-9 pin 4 DTR  ─────> pin 2 RX / UART1 RX
 UART1 RTS / DE-9 pin 7 RTS ─────> pin 1 DCD / UART2 CTS
 ```
 
-Run `rts-flow-test`. GPIO7 is temporarily routed from UART2 TX through the MAX3243 DTR driver. GPIO4 receives UART1 RTS through the DCD receiver and is simultaneously routed to UART2 CTS. This creates a complete hardware-controlled flow loop without an external serial peer.
+Run `debug rts-flow-test`. GPIO7 is temporarily routed from UART2 TX through the MAX3243 DTR driver. GPIO4 receives UART1 RTS through the DCD receiver and is simultaneously routed to UART2 CTS. This creates a complete hardware-controlled flow loop without an external serial peer.
 
 The test queues 4096 bytes from UART2 but initially does not read UART1. UART1's receive ring eventually fills, its hardware FIFO crosses the configured threshold, and UART1 automatically deasserts RTS. That state passes through the physical pin 7 to pin 1 jumper and blocks UART2 through CTS. The firmware then drains UART1, which must automatically reassert RTS and allow UART2 to finish.
 
@@ -195,16 +195,16 @@ The test queues 4096 bytes from UART2 but initially does not read UART1. UART1's
 
 ### Manual voltage and polarity checks
 
-With no DE-9 loopback jumpers installed, use the static `drivers` command and measure each driven output relative to DE-9 pin 5 (`GND`):
+With no DE-9 loopback jumpers installed, use the static `debug drivers` command and measure each driven output relative to DE-9 pin 5 (`GND`):
 
 ```text
-drivers 0 0 0
+debug drivers 0 0 0
 ```
 
 Each of pins 3, 4, and 7 should be at a positive RS-232 voltage. Then run:
 
 ```text
-drivers 1 1 1
+debug drivers 1 1 1
 ```
 
 Each output should be at a negative RS-232 voltage. Exact values vary with supply, load, meter, and charge-pump behavior; polarity is the primary check. The firmware leaves all outputs at logic 1 after automated tests.
@@ -212,14 +212,14 @@ Each output should be at a negative RS-232 voltage. Exact values vary with suppl
 ### Recommended test order
 
 1. Start with no DE-9 jumpers and run `status`.
-2. Use `drivers 0 0 0` and `drivers 1 1 1` for the three output-polarity measurements.
-3. Power down, install configuration A, power up, and run `loopback-a`.
-4. With configuration A still installed and no external peer, run `valid-test`.
-5. Keep only the pin 3 to pin 2 jumper and run a basic test such as `uart-loopback 9600 8N1 256`.
-6. If that passes, run `uart-suite`.
-7. Power down, replace the jumpers with configuration B, power up, and run `loopback-b`.
-8. Power down, install configuration C, power up, and run `cts-flow-test`.
-9. Power down, install configuration D, power up, and run `rts-flow-test`.
+2. Use `debug drivers 0 0 0` and `debug drivers 1 1 1` for the three output-polarity measurements.
+3. Power down, install configuration A, power up, and run `debug loopback-a`.
+4. With configuration A still installed and no external peer, run `debug valid-test`.
+5. Keep only the pin 3 to pin 2 jumper and run a basic test such as `debug uart-loopback 9600 8N1 256`.
+6. If that passes, run `debug uart-suite`.
+7. Power down, replace the jumpers with configuration B, power up, and run `debug loopback-b`.
+8. Power down, install configuration C, power up, and run `debug cts-flow-test`.
+9. Power down, install configuration D, power up, and run `debug rts-flow-test`.
 
 RTS and CTS remain ordinary GPIO signals during static and basic UART loopback tests. Only the two dedicated flow-control commands hand them to UART peripherals. Every test shuts the MAX3243 down while changing GPIO-matrix routing and restores all outputs to static logic 1 afterward.