Commander1024
c257158ada
Align component groups, repair affected routing, and add preservation audits. Assign the confirmed U2 footprint and update pull-ups to 2 kΩ across design files. Document user acceptance, switch to an A3 worksheet, and refresh PCB exports.
140 lines
7.2 KiB
Python
140 lines
7.2 KiB
Python
#!/usr/bin/env python3
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"""Read-only PCB checks and fresh KiCad reports; does not regenerate or save PCB.
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Requires KiCad's pcbnew binding in system Python. Schematic footprint parity
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must be clean, including the user-confirmed U2 reference footprint assignment.
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"""
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import hashlib
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import json
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from pathlib import Path
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import subprocess
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import xml.etree.ElementTree as ET
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import pcbnew as p
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from update_u1_graphics import verify
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ROOT=Path(__file__).resolve().parent
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PCB=ROOT/"serial-carrier.kicad_pcb"
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OUT=ROOT/"validation"
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def run(*args):
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subprocess.run(args,check=True,cwd=ROOT)
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run("kicad-cli","sch","export","netlist","--format","kicadxml","-o",str(OUT/"pcb-source-netlist.xml"),str(ROOT/"serial-carrier.kicad_sch"))
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run("kicad-cli","pcb","drc","--format","json","--all-track-errors","--severity-all","--schematic-parity","-o",str(OUT/"pcb-parity-drc.json"),str(PCB))
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board=p.LoadBoard(str(PCB))
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verify(board)
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from update_presentation import expected_tree, CAPTION
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from validate_u1_update import parse, canonical
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tree=parse(PCB)
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assert ['paper', '"A3"'] in tree, "A3 worksheet required to clear the title block"
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assert canonical(expected_tree(tree)) == canonical(tree), "Stale presentation labels"
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assert board.GetTitleBlock().GetComment(0) == ""
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assert any(isinstance(g,p.PCB_TEXT) and g.GetText()==CAPTION for g in board.GetDrawings())
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source=ET.parse(OUT/"pcb-source-netlist.xml").getroot()
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comps={c.get("ref"):c for c in source.findall("components/comp")}
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footprints={f.GetReference():f for f in board.GetFootprints()}
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assert set(footprints)==set(comps)|{"H1","H2","H3","H4"}
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assert board.GetCopperLayerCount()==2
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assert p.ToMM(board.GetDesignSettings().GetBoardThickness())==1.6
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outline=[d for d in board.GetDrawings() if d.GetLayer()==p.Edge_Cuts]
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assert len(outline)==6
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points={(round(p.ToMM(v.x)-100,5),round(p.ToMM(v.y)-100,5)) for d in outline for v in (d.GetStart(),d.GetEnd())}
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expected_outline=[(36,0),(82,0),(82,80),(0,80),(0,19),(36,19)]
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assert points==set(expected_outline)
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expected_edges={frozenset((a,b)) for a,b in zip(expected_outline,expected_outline[1:]+expected_outline[:1])}
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actual_edges={frozenset((round(p.ToMM(v.x)-100,5),round(p.ToMM(v.y)-100,5))
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for v in (d.GetStart(),d.GetEnd())) for d in outline}
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assert actual_edges==expected_edges
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placements={"U1":(8,23),"U2":(43,26.670),"DS1":(43.97,36),
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"R1":(42.16,32.6685),"R2":(53.16,32.6685),"R3":(64.16,32.6685),
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"SW1":(41.72,68),"SW2":(53.72,68),"SW3":(65.72,68),
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"H1":(3.5,22.5),"H2":(3.5,75),"H3":(78,4),"H4":(78,76)}
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for ref,(x,y) in placements.items():
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position=footprints[ref].GetPosition()
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assert position.x==p.FromMM(x+100) and position.y==p.FromMM(y+100),ref
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assert footprints[ref].GetOrientationDegrees()==0,ref
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assert len(board.Zones())==1
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reserve=board.Zones()[0]
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assert reserve.GetIsRuleArea() and reserve.IsOnLayer(p.F_Cu) and reserve.IsOnLayer(p.B_Cu)
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assert reserve.GetDoNotAllowTracks() and reserve.GetDoNotAllowVias() and reserve.GetDoNotAllowZoneFills()
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contour=reserve.Outline().COutline(0)
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assert {(p.ToMM(contour.CPoint(i).x),p.ToMM(contour.CPoint(i).y)) for i in range(contour.PointCount())}=={(110,119),(131,119),(131,132),(110,132)}
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# Reference bare-PCB front is 26.670 mm above the U2 pad-row origin.
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u2_front=p.ToMM(footprints['U2'].GetPosition().y)-26.670
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assert abs(u2_front-100)<1e-6
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assert any(isinstance(g,p.PCB_SHAPE) and g.GetLayer()==p.F_Fab and
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g.GetShape()==p.SHAPE_T_SEGMENT and
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g.GetStart().y==p.FromMM(100) and g.GetEnd().y==p.FromMM(100)
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for g in footprints['U2'].GraphicalItems()), 'U2 bare-PCB front not flush'
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assert max(x for x,y in points)-min(x for x,y in points)==82
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assert max(y for x,y in points)-min(y for x,y in points)==80
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padnets={}
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for net in source.findall("nets/net"):
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for node in net.findall("node"):
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padnets[(node.get("ref"),node.get("pin"))]=net.get("name")
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seen=set()
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for ref,comp in comps.items():
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fp=footprints[ref]
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assert fp.GetValue()==comp.findtext("value"),ref
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assert fp.GetPath().AsString().endswith("/"+comp.findtext("tstamps")),ref
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wanted=comp.findtext("footprint")
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if ref=="U2":
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assert wanted=="Carrier:MAX3243_Reference_Provisional"
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assert fp.GetFPIDAsString()=="Carrier:MAX3243_Reference_Provisional"
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else:
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assert fp.GetFPIDAsString()==wanted,ref
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for pad in fp.Pads():
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if not pad.GetNumber():
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continue
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key=ref,pad.GetNumber()
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assert pad.GetNetname()==padnets[key],(key,pad.GetNetname(),padnets[key])
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seen.add(key)
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assert seen==set(padnets),"Missing or extra electrical pads"
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for ref in ("H1","H2","H3","H4"):
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assert footprints[ref].IsBoardOnly()
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pads=list(footprints[ref].Pads())
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assert len(pads)==1 and pads[0].GetDrillSize().x==p.FromMM(3.2)
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assert pads[0].GetAttribute()==p.PAD_ATTRIB_NPTH
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tracks=list(board.GetTracks())
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assert tracks,"Draft unexpectedly unrouted"
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for track in tracks:
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if isinstance(track,p.PCB_VIA):
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assert track.GetDrillValue()==p.FromMM(0.3)
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assert track.GetWidth(p.F_Cu)==p.FromMM(0.7)
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else:
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assert track.GetLayer() in (p.F_Cu,p.B_Cu)
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expected=0.5 if track.GetNetname() in ("/+3V3","/GND") else 0.25
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assert track.GetWidth()==p.FromMM(expected)
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report=json.loads((OUT/"pcb-parity-drc.json").read_text())
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assert not report["violations"],report["violations"]
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assert not report["unconnected_items"],report["unconnected_items"]
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parity=report["schematic_parity"]
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assert not parity,parity
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summary={
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"carrier_bounds_mm":[82,80],
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"outline_local_mm":expected_outline,
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"placements_local_mm":placements,
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"rf_reserve_absolute_mm":[110,119,131,132],
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"u2_bare_pcb_front_local_y_mm":round(u2_front-100,6),
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"nominal_user_confirmed_rs232_metal_mm":{"shell_overhang":3.870,"hex_mouth_overhang":2.870,"flange_front_inset":1.930},
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"tracks":sum(not isinstance(t,p.PCB_VIA) for t in tracks),
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"vias":sum(isinstance(t,p.PCB_VIA) for t in tracks),
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"copper_layers":2,
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"draft_thickness_mm":1.6,
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"electrical_footprints":len(comps),
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"proposed_M3_mounts":4,
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"physical_DRC_violations":0,
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"unconnected_items":0,
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"schematic_pad_nets_match":True,
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"schematic_parity_violations":0,
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"project_settings_sha256":hashlib.sha256((ROOT/'serial-carrier.kicad_pro').read_bytes()).hexdigest(),
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"ignored_DRC_checks":report["ignored_checks"],
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"user_accepted":["module dimensions/visual fit and USB clearance", "male pinout/header/footprint and pin-by-pin review", "M3 carrier/module and M2 display hardware", "RF keepout and power/ground routing"],
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"not_independently_verified":["reported 10 mm assembled module elevation", "regulator margin", "USB backfeed safety", "OLED onboard pull-up resistance/rail", "manufacturer RF qualification", "fabrication process/certification"],
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"new_hardware_tests":False,
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}
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(OUT/"pcb-validation-summary.json").write_text(json.dumps(summary,indent=2)+"\n")
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print("PCB draft verified: 82 x 80 mm; 2 copper layers; 0 physical DRC violations; 0 unrouted.")
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print("All schematic pad nets and footprint assignments match. Zero schematic parity violations.")
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print("Not fabrication-ready; see ../../docs/devel/hardware/PCB/pcb-draft-notes.md and ignored checks in the DRC report.")
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