ESP32_Serial_Swiss_Army_Knife/hardware/PCB/adafruit-research.md

Adafruit MAX3243 breakout: authoritative CAD header research

Research date: 2026-09-20. Scope: source retrieval and pad/geometry extraction only; no project schematic or layout modified.

Critical product distinction

Product 5988 is the DE-9 female version. The male version is product 6253. The product-5988 page's male variant link goes to /product/6253; each product description explicitly identifies its connector gender. Both link to the same Learn guide. Do not describe the downloaded CAD as verified male-specific CAD: its connector is X2, value DE9-F, package F09HP, and the repository README identifies product 5988.

The exact header map below is proven for the published 5988 board. It is useful reference for the family, but identical male-board geometry/pad numbering has not been established by a male-specific CAD file or physical measurement. Confirm the actual 6253 module before releasing a male carrier footprint. No inference from connector gender or a generic DE-9 footprint is substituted for that check.

Provenance and downloaded originals

Authoritative chain:

1. Adafruit Learn downloads links to the Eagle repository below, a TI datasheet, fab print and 3D models.
2. Adafruit PCB repository.
3. Retrieved main commit 63c6200bb3ef17d491089cfa6441b1810d79bb20, committed 2024-08-12T22:42:27Z. All four local originals were downloaded from this immutable revision, not a moving branch.
4. Product 5988, female, product 6253, male, and Learn pinouts corroborate identity and signal names.

Local files in reference/, unchanged upstream contents:

File	SHA-256
Adafruit RS-232 Full Pinout Level-Shifter Breakout.brd	6a7b35ef909f5a2d243c326c34db3957aaa01275bf2aac8e0c749ff18162e870
Adafruit RS-232 Full Pinout Level-Shifter Breakout.sch	4efbbe0ad14194e4e4563dd5f7dac007dfd52eba636f7390ffb822f3e81cd896
README.md	2825ba741a8ce83abdaf2c7cb9170641473357630ccbee40a0016dcdb5cd80bb
license.txt	075dad5e5fc96c27014fabc269f4f5732909cffd178a486f546d982b6cf86b74

Raw URL prefix for each filename (URL-encode spaces):

https://raw.githubusercontent.com/adafruit/Adafruit-RS-232-Level-Shifter-Breakout-PCB/63c6200bb3ef17d491089cfa6441b1810d79bb20/

License: upstream license.txt is Creative Commons Attribution-ShareAlike 3.0 Unported (CC BY-SA 3.0). README attribution: “Designed by Limor Fried/Ladyada for Adafruit Industries.” README explicitly requires all its preceding text in redistribution; the full original README and license are therefore retained. Preserve these notices when redistributing CAD and comply with applicable attribution/share-alike obligations for adaptations. The CAD-derived content of this report is attributed to that design and provided under CC BY-SA 3.0.

The guide also links 5988 3D CAD. Its directory listing contains .f3d, .step, .stl, and .jpg; these were not downloaded or used for measurements, and their licensing was not independently assessed. No male-specific 3D model was verified in this research.

Exact header numbering and net map

Source: Eagle XML drawing/board/elements/element[@name='JP2'], embedded microbuilder package 1X12_ROUND_76MIL, and drawing/board/signals/signal/contactref. Cross-checked against schematic JP2, deviceset HEADER-1X12, selected device 76MIL: symbol pin N maps directly to physical pad N.

Viewing convention: component/top view, DE-9 pointing toward the top of the page (+Y), logic header along the bottom. X increases rightward, Y upward. The origin is the lower-left bounding-box corner of the bare PCB (the corner itself is rounded). These are Eagle board coordinates in millimetres, not a mating-face view and not a bottom view.

                  DE-9 / +Y
           +-----------------------+
           |                       |
           |   o               o   |  module mounting holes
           |                       |
           | 1  2  3 ...       12   |  JP2, y = 2.667 mm
           +-----------------------+
             Vin                OFF
                    +X ->

JP2 physical pad	Label / function	CAD net	X (mm)	Y (mm)	MAX3243 IC1 pad	DE-9 X2 pad via level shifter
1	Vin	VCC	1.905	2.667	26	—
2	GND	GND	4.445	2.667	25	5 (direct ground)
3	DCD	DCD	6.985	2.667	15	1
4	RX	RXD	9.525	2.667	16	2
5	TX	TXD	12.065	2.667	13	3
6	DTR	DTR	14.605	2.667	14	4
7	DSR	DSR	17.145	2.667	17	6
8	RTS	RTS	19.685	2.667	12	7
9	CTS	CTS	22.225	2.667	19	8
10	RI	RI	24.765	2.667	18	9
11	VLD	!INVALID	27.305	2.667	21	—
12	OFF	!FORCEOFF	29.845	2.667	22	—

Left-to-right order: Vin GND DCD RX TX DTR DSR RTS CTS RI VLD OFF. This is physical pad order, not the order of rows in the project's wiring table.

At the logic header, TX/DTR/RTS are inputs to the MAX3243; RX/DCD/DSR/CTS/RI are outputs from it. Schematic gates explicitly map TX to T2IN, DTR to T1IN, RTS to T3IN, RX to R4OUT, DCD to R5OUT, DSR to R3OUT, CTS to R1OUT and RI to R2OUT. RS-232 and logic signal nets are separated by the chip; matching signal names do not mean direct continuity.

OFF is active low (!FORCEOFF, IC1 pad 22) with 10 kΩ pull-up R1 to VCC. The Learn pinout page agrees. The upstream README and shop prose incorrectly say high shuts it down; do not propagate that prose error. VLD is !INVALID, high on valid input detection. Use 3.3 V Vin for this project's ESP32 interface, as already required by docs/wiring.md.

Exact published PCB geometry

All figures below are nominal CAD dimensions, not measured tolerances.

Logic header JP2

• Single row, 12 plated through-hole pads at 2.54 mm (0.100 inch) pitch.
• Element origin (15.875, 2.667); no element rotation or mirroring (R0).
• Package local pad centres: x = -13.970 + 2.540 × (N - 1), y = 0, N = 1…12.
• Board coordinates: x = 1.905 + 2.540 × (N - 1), y = 2.667.
• First-to-last centre span 27.940 mm (1.100 inch).
• All holes: 1.000 mm drill, explicit 1.9304 mm (76 mil) round copper diameter. Each pad has rot="R90"; that does not rotate the header row or change a round pad's outline.
• Both end pad centres are 1.905 mm from the corresponding vertical board edge.
• Row is 2.667 mm (0.105 inch) above the lower bounding-box edge.
• No square pad-1 marker is defined by this package: identify pad 1 using Vin and the stated view, not assumed square copper.

Bare-board outline and mounting holes

Source: drawing/board/plain/wire[@layer='20'] and mounting-hole element/package definitions.

• Bare PCB bounding box: 31.750 mm X × 29.337 mm Y (1.250 × 1.155 inches), X = 0…31.750, Y = 0…29.337.
• Straight top edge (0,29.337) to (31.750,29.337); square top corners.
• Bottom corners: 2.540 mm radius, defined by 90° arcs (0,2.540) → (2.540,0) and (29.210,0) → (31.750,2.540).
• Bottom straight edge: X = 2.540…29.210 at Y = 0.
• Module mounting holes: U$2 at (3.810, 11.430) and U$3 at (27.940, 11.430).
• Both use MOUNTINGHOLE_3.0_PLATEDTHIN, pad P$1, 3.000 mm drill / 3.600 mm copper diameter. They are plated pads, not anonymous NPTH holes, and neither appears in the board's signal contactrefs.
• Hole centre spacing 24.130 mm (0.950 inch); hole row is 8.763 mm above the header row.

For a carrier footprint using header pad 1 as (0,0) with Y still upward:

• Header pads: (2.540 × (N - 1), 0).
• Mounting hole centres: (1.905, 8.763) and (26.035, 8.763).
• Bare-board bounding box: X = −1.905…29.845, Y = −2.667…26.670; retain corner arcs described above.

If the destination CAD uses screen coordinates with Y downward, transform Y deliberately; do not silently mirror physical pad numbering. The placement side and whether the module faces up or down must be fixed before generating a carrier footprint.

DE-9 on the downloaded female CAD (not male qualification)

X2 origin (15.875,17.907), R0, package F09HP, value DE9-F.

X2 pad	Board X (mm)	Board Y (mm)	CAD net
1	10.3886	16.637	RS_DCD
2	13.1318	16.637	RS_RXD
3	15.8750	16.637	RS_TXD
4	18.6182	16.637	RS_DTR
5	21.3614	16.637	GND
6	11.7602	19.177	RS_DSR
7	14.5034	19.177	RS_RTS
8	17.2466	19.177	RS_CTS
9	19.9898	19.177	RS_RI
G1	3.3528	17.907	no signal contactref
G2	28.3972	17.907	no signal contactref

Signal holes have 1.016 mm drill and 1.778 mm octagonal copper; shell/mechanical pads G1/G2 have 3.302 mm drill and 5.080 mm copper, spaced 25.0444 mm. Shell pads are not shown tied to GND by signal contactrefs; DE-9 pin 5 is grounded. These are PCB solder-tail coordinates, not front-face pin coordinates.

The connector package's layer-21 drawing reaches local Y = 17.907, hence board Y = 35.814, beyond the board's Y = 29.337. This is library drawing evidence, not a validated mechanical envelope. Do not size an enclosure from silkscreen. Product pages list assembled dimensions of 33.6 × 32.0 × 14.1 mm (5988) and 33.7 × 31.8 × 14.2 mm (6253), with no coordinate/tolerance definition; these do not replace a male-specific mechanical drawing, and differ from the female library drawing extent.

Validation and next-use boundary

• Parsed the actual Eagle board and schematic XML successfully using Python's standard-library XML parser.
• Joined package pad names to board signal contactrefs, applied JP2's unrotated element translation, and cross-checked schematic header numbering/net assignments.
• Extracted outline arcs, mounting-hole package dimensions, and connector pad data directly; no dimensions inferred from product photos.
• Recorded SHA-256 hashes of the downloaded originals.
• No firmware build or hardware tests performed: this task changed research/reference files only.
• Ready: exact published 5988 header map, pad centres, board outline and hole coordinates for CAD reference.
• Still required for a male-module carrier release: establish that the purchased module is 6253, verify its header order and mounting geometry against male-specific CAD or the physical module, and verify connector overhang, mating clearance, module height and mounting orientation. The shared guide alone is insufficient proof of identical male geometry.