Commander1024
60c1e279d6
Introduce an editable KiCad 10 schematic and routed two-layer 82 × 80 mm layout with local provisional footprints, validation tooling, and component research. Keep the RS-232 male-module mapping and mechanical clearances explicitly provisional pending hardware verification.
222 lines
9.3 KiB
Python
222 lines
9.3 KiB
Python
#!/usr/bin/env python3
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"""Create the compact placement draft from a fresh KiCad XML netlist.
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Requires system Python + pcbnew. Refuses to overwrite an existing PCB unless
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--overwrite is explicit. This is a draft generator, not a manufacturing tool.
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Does not modify the schematic or footprint libraries. KiCad SaveBoard also saves
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PCB design settings into the project; close the project before regeneration.
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"""
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import argparse
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import json
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from pathlib import Path
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import re
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import subprocess
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import xml.etree.ElementTree as ET
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import pcbnew as p
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ROOT = Path(__file__).resolve().parent
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PCB = ROOT / "serial-carrier.kicad_pcb"
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LIBS = Path("/usr/share/kicad/footprints")
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ORIGIN = (100, 100)
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OUTLINE = [(0,0), (82,0), (82,80), (36,80), (36,61), (0,61)]
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PLACEMENT = {
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"U1": ("Carrier:HW678_2x22_Provisional", 8, 4),
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"U2": ("Carrier:MAX3243_Reference_Provisional", 43, 30),
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"DS1": ("Carrier:OLED_26mm_I2C_Provisional", 43, 36),
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"R1": ("Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal", 43, 34),
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"R2": ("Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal", 54, 34),
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"R3": ("Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal", 65, 34),
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"SW1": ("Button_Switch_THT:SW_TH_Tactile_Omron_B3F-100x", 43, 68),
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"SW2": ("Button_Switch_THT:SW_TH_Tactile_Omron_B3F-100x", 55, 68),
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"SW3": ("Button_Switch_THT:SW_TH_Tactile_Omron_B3F-100x", 67, 68),
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}
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MOUNTS = [(3.5,3.5), (3.5,56), (78,4), (78,76)]
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# Deliberate allocation, NOT a measured antenna envelope or an RF guarantee.
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RF_RESERVE = [(10,0), (31,0), (31,13), (10,13)]
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def mm(v):
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return p.FromMM(v)
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def xy(x,y):
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return p.VECTOR2I(mm(x+ORIGIN[0]), mm(y+ORIGIN[1]))
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def text(board, value, x, y, layer=p.F_SilkS, size=1):
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item = p.PCB_TEXT(board)
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item.SetText(value)
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item.SetPosition(xy(x,y))
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item.SetLayer(layer)
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item.SetTextSize(p.VECTOR2I(mm(size),mm(size)))
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item.SetTextThickness(mm(0.15))
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board.Add(item)
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return item
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def polygon(zone, points):
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poly=zone.Outline()
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poly.NewOutline()
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for x,y in points:
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pt=xy(x,y)
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poly.Append(pt.x,pt.y)
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def load(lib_id):
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lib,name=lib_id.split(":",1)
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folder=ROOT / "Carrier.pretty" if lib=="Carrier" else LIBS / (lib+".pretty")
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fp=p.FootprintLoad(str(folder),name)
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if fp is None:
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raise RuntimeError("Cannot load "+lib_id)
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fp.SetFPIDAsString(lib_id)
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return fp
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def quiet_footprint(fp):
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# Retain all mechanical geometry, but replace sprawling research annotation
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# text with concise board annotations. Libraries are never modified.
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for graphic in list(fp.GraphicalItems()):
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if isinstance(graphic,p.PCB_TEXT):
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fp.Remove(graphic)
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fp.Value().SetVisible(False)
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fp.Reference().SetTextSize(p.VECTOR2I(mm(1),mm(1)))
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fp.Reference().SetTextThickness(mm(0.15))
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fp.Reference().SetLayer(p.F_SilkS)
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def copy_schematic_fields(fp, component):
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for field in component.findall("fields/field"):
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name=field.get("name")
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if name in ("Reference", "Value", "Footprint"):
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continue
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fp.SetField(name, field.text or "")
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fp.GetField(name).SetVisible(False)
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def configure_draft_netclasses():
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# SaveBoard creates the project defaults. Align future interactive routing
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# with the draft's physical minimum widths and its explicit power routing.
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path=ROOT/"serial-carrier.kicad_pro"
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project=json.loads(path.read_text())
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settings=project["net_settings"]
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default=next(c for c in settings["classes"] if c["name"]=="Default")
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default.update(clearance=0.25, track_width=0.25, via_diameter=0.7, via_drill=0.3)
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power=dict(default, name="Power", priority=0, track_width=0.5, diff_pair_width=0.25)
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settings["classes"]=[c for c in settings["classes"] if c["name"]!="Power"]+[power]
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patterns=[v for v in settings.get("netclass_patterns",[]) if v["pattern"] not in ("/+3V3","/GND")]
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settings["netclass_patterns"]=patterns+[{"netclass":"Power","pattern":name} for name in ("/+3V3","/GND")]
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path.write_text(json.dumps(project,indent=2)+"\n")
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def main():
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parser=argparse.ArgumentParser(description=__doc__)
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parser.add_argument("--overwrite",action="store_true")
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args=parser.parse_args()
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if PCB.exists() and not args.overwrite:
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parser.error("PCB exists; preserve manual edits or explicitly use --overwrite")
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if any(ROOT.glob("~serial-carrier.*.lck")):
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parser.error("Project is open in KiCad; close it before regenerating PCB/settings")
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netfile=ROOT / "validation/pcb-source-netlist.xml"
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subprocess.run(["kicad-cli","sch","export","netlist","--format","kicadxml","-o",str(netfile),str(ROOT/"serial-carrier.kicad_sch")],check=True)
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source=ET.parse(netfile).getroot()
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components={c.get("ref"):c for c in source.findall("components/comp")}
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assert set(components)==set(PLACEMENT), "Schematic component set changed; review layout"
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schematic=ROOT.joinpath("serial-carrier.kicad_sch").read_text()
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root_uuid=re.search(r'\(uuid "?([a-f0-9-]{36})"?\)',schematic).group(1)
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board=p.BOARD()
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board.SetCopperLayerCount(2)
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settings=board.GetDesignSettings()
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settings.SetBoardThickness(mm(1.6))
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settings.m_MinClearance=mm(0.25)
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settings.m_CopperEdgeClearance=mm(0.5)
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settings.m_HoleClearance=mm(0.25)
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settings.m_TrackMinWidth=mm(0.25)
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settings.m_ViasMinSize=mm(0.7)
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# SaveBoard persists these proposed draft rules into the project settings.
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title=board.GetTitleBlock()
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title.SetTitle("Serial Swiss Army Knife - 82x80 mm carrier draft")
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title.SetRevision("A0 DRAFT")
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title.SetComment(0,"NOT FOR FABRICATION - male module / USB / antenna geometry unverified")
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pad_nets={}
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for source_net in source.findall("nets/net"):
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net=p.NETINFO_ITEM(board,source_net.get("name"))
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board.Add(net)
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for node in source_net.findall("node"):
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pad_nets[node.get("ref"),node.get("pin")]=(net,node)
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for ref,(lib_id,x,y) in PLACEMENT.items():
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comp=components[ref]
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if ref != "U2":
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assert comp.findtext("footprint")==lib_id,(ref,"Schematic footprint changed")
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fp=load(lib_id)
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fp.SetReference(ref)
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fp.SetValue(comp.findtext("value"))
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path=p.KIID_PATH()
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path.push_back(p.KIID(root_uuid))
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path.push_back(p.KIID(comp.findtext("tstamps")))
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fp.SetPath(path)
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fp.SetSheetfile("serial-carrier.kicad_sch")
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fp.SetSheetname("serial-carrier")
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fp.SetPosition(xy(x,y))
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board.Add(fp)
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quiet_footprint(fp)
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copy_schematic_fields(fp,comp)
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if ref=="U1":
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fp.Reference().SetPosition(xy(20.7,25))
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elif ref=="U2":
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fp.Reference().SetPosition(xy(56.97,18))
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elif ref=="DS1":
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fp.Reference().SetPosition(xy(56,49))
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elif ref.startswith("SW"):
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fp.Reference().SetPosition(xy(x+3.25,y-2))
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else:
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fp.Reference().SetLayer(p.F_Fab)
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fp.Reference().SetPosition(xy(x+3.81,y-1.6))
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for pad in fp.Pads():
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key=ref,pad.GetNumber()
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if pad.GetNumber():
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net,node=pad_nets[key]
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pad.SetNet(net)
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pad.SetPinFunction(node.get("pinfunction", ""))
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pad.SetPinType(node.get("pintype", "passive"))
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for i,(x,y) in enumerate(MOUNTS,1):
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fp=load("MountingHole:MountingHole_3.2mm_M3")
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fp.SetReference("H"+str(i))
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fp.SetValue("M3 mounting proposal / 3.2mm")
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fp.SetBoardOnly(True)
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fp.SetExcludedFromBOM(True)
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fp.SetExcludedFromPosFiles(True)
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fp.SetPosition(xy(x,y))
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board.Add(fp)
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quiet_footprint(fp)
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fp.Reference().SetVisible(False)
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for a,b in zip(OUTLINE,OUTLINE[1:]+OUTLINE[:1]):
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edge=p.PCB_SHAPE(board)
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edge.SetShape(p.SHAPE_T_SEGMENT)
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edge.SetStart(xy(*a)); edge.SetEnd(xy(*b))
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edge.SetLayer(p.Edge_Cuts); edge.SetWidth(mm(0.05))
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board.Add(edge)
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reserve=p.ZONE(board)
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reserve.SetIsRuleArea(True)
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layers=p.LSET(); layers.AddLayer(p.F_Cu); layers.AddLayer(p.B_Cu)
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reserve.SetLayerSet(layers)
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reserve.SetZoneName("PROVISIONAL RF RESERVE - verify actual antenna clearance")
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reserve.SetDoNotAllowTracks(True); reserve.SetDoNotAllowVias(True)
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reserve.SetDoNotAllowZoneFills(True); reserve.SetDoNotAllowPads(True)
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reserve.SetDoNotAllowFootprints(False) # the module itself spans this region
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polygon(reserve,RF_RESERVE)
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board.Add(reserve)
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text(board,"RF RESERVE",20.5,7,p.Dwgs_User,1.2)
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text(board,"VERIFY ANTENNA",20.5,10,p.Dwgs_User,1)
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text(board,"ESP32 HW678",20.7,29)
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text(board,"USB ACCESS - VERIFY",18,64,p.Dwgs_User,1)
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text(board,"DE-9 OUT / VERIFY MALE",56.97,1.5,p.Dwgs_User,1)
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text(board,"MAX3243 REF",56.97,21)
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text(board,"26mm OLED",56,52)
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for label,x in zip(("BACK","SELECT","NEXT"),(46.25,58.25,70.25)):
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text(board,label,x,75, size=0.9)
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text(board,"DRAFT - NOT FOR FAB",56,78,size=0.9)
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text(board,"82 x 80 mm / 2 copper layers",41,-5,p.Dwgs_User,1.5)
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text(board,"Carrier envelope only; module overhang and connector clearance not qualified",41,-2.5,p.Dwgs_User,0.9)
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board.BuildConnectivity()
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p.SaveBoard(str(PCB),board)
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configure_draft_netclasses()
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print("Created",PCB,"with 9 circuit footprints, 4 proposed M3 mounts, 2 copper layers.")
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print("Placement draft only. Board-only U2 footprint is a female-CAD reference, not male qualification.")
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if __name__=="__main__":
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main()
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