Commander1024/ESP32_Serial_Swiss_Army_Knife

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Commander1024 60c1e279d6 Add KiCad module carrier PCB draft

Introduce an editable KiCad 10 schematic and routed two-layer 82 × 80 mm
layout with local provisional footprints, validation tooling, and
component
research. Keep the RS-232 male-module mapping and mechanical clearances
explicitly provisional pending hardware verification.

2026-09-20 23:14:01 +02:00

9.6 KiB

Raw Blame History

Compact two-layer PCB — A0 draft

Open serial-carrier.kicad_pcb in KiCad 10. The routed board belongs to the existing serial-carrier.kicad_pro / .kicad_sch project. Not for fabrication. No Gerbers, production drills or manufacturing archive were generated.

Size and placement

Carrier bounding dimensions: 82 × 80 mm, within the requested 100 × 100 mm.
Two copper layers, F.Cu and B.Cu. All components mount on the front.
Proposed 1.6 mm carrier thickness; fabrication stackup/process not selected.
Stepped outline: a 36 × 19 mm lower-left cutaway leaves cable space below the ESP32 while the OLED/buttons occupy the deeper right-hand section.
Module and mating-plug overhangs are not included in the carrier dimensions. The final complete assembly/enclosure envelope still needs measurement.

Coordinates in the following table are local millimetres from the carrier's upper-left corner, X right/Y down, viewed from the component side. In the KiCad file add (100, 100) mm to obtain absolute board coordinates. All footprints are unrotated; their origins are defined in the footprint notes, not necessarily component body corners.

Reference	Local origin (X, Y)	Placement
U1	(8, 4)	ESP32 left header pin 1; antenna toward upper edge, USB toward cutaway
U2	(43, 30)	MAX3243 header pin 1; DE-9 toward upper edge
DS1	(43, 36)	OLED module upper-left PCB corner; display faces up
R1 / R2 / R3	(43 / 54 / 65, 34)	Axial pull-ups in the gap between RS-232 and OLED
SW1 / SW2 / SW3	(43 / 55 / 67, 68)	Back, select, next below display; switch pad 1 origins
H1	(3.5, 3.5)	Proposed case mounting hole
H2	(3.5, 56)	Proposed case mounting hole
H3	(78, 4)	Proposed case mounting hole
H4	(78, 76)	Proposed case mounting hole

Outline vertices: (0,0), (82,0), (82,80), (36,80), (36,61), (0,61), closed. The board area is 58.76 cm²; its bounding rectangle is 65.6 cm².

H1–H4 are proposed Ø3.2 mm NPTH M3 clearance holes, not a previously agreed case specification. They are marked board-only and excluded from the electrical BOM. The OLED and RS-232 module mounting holes are additional, separate holes. Screw heads, spacers, heat-set inserts, tool access and underside lead clearance must be checked against the final case and assembly heights. No insert dimensions or module stand-off heights are assumed.

Routing and electrical status

The PCB contains actual copper, not just ratsnest placement:

All 38 required physical-pad spanning connections across 17 connected nets routed, including both duplicated pads of each switch contact.
569 segments, signal width 0.25 mm, 3.3 V and GND width 0.50 mm.
20 through vias, 0.70 mm copper / 0.30 mm drill.
No copper pours; ground is explicitly routed. This is an initial routing solution, not a reviewed return-current/EMI or power-integrity design.
Proposed minimum different-net clearance 0.25 mm and copper-edge clearance 0.50 mm. These are selected draft design rules, not fabrication qualification.
Project netclasses align interactive routing defaults with the draft: Default uses 0.25 mm tracks / 0.25 mm clearance, while Power matches /+3V3 and /GND with 0.50 mm tracks. Both use 0.70 / 0.30 mm vias.
Schematic pad-net assignments, component values and UUID linkage are retained. U1's intentionally unused GPIO/USB/UART0/5 V header pads remain unused.

The bounded draft router prioritizes connectivity and conservative geometric clearance, not optimal trace topology. Do not treat DRC passage as evidence of current-carrying capacity, supply stability, I²C signal quality or EMC compliance.

Explicit provisional mechanical choices

ESP32 and RF

A two-layer no-tracks/no-vias/no-pads/no-zone-fill rule area reserves local X=10…31 mm, Y=0…13 mm toward the antenna. This is a deliberate carrier design allocation, not a measured antenna envelope or a manufacturer RF keepout. The module itself may span the rule area; footprint placement is not forbidden. No carrier copper enters the reserve, but copper runs close to its boundary.

U1's exact PCB/antenna/USB offsets are still unmeasured. The intended antenna overhang and USB access must be checked with the actual board and a printed placement template. Move U1, change the edge or enlarge the reserve if required. Missing RF clearance cannot be signed off from the current footprint alone.

RS-232

U2 uses the new Carrier:MAX3243_Reference_Provisional footprint on the PCB only. Its bare-module outline/header/holes are adapted from published female 5988 CAD for the intended male 6253 module. The user reports identical dimensions, but the male header map and assembled DE-9 envelope are still unverified. See rs232-footprint-notes.md and its CC BY-SA attribution.

The schematic footprint remains intentionally blank, preserving its caution and avoiding edits to the schematic that was open in KiCad. Consequently there is one known schematic-parity warning: U2 footprint differs from the empty schematic assignment. This is not excluded/suppressed, and is not a net mismatch. Once the male footprint is qualified, explicitly assign it in the schematic before relying on Update PCB from Schematic to manage U2's footprint.

OLED and controls

OLED geometry, including its display boundary, is the user-fit-verified geometry. The module schematic/library files are unchanged. The new overall placement still needs an assembly fit check: adjacent resistor bodies, module underside parts, header/socket bodies, button actuation and finger/plunger clearance are not represented by complete assembly courtyards. In particular the axial resistors are tightly packed between the module outlines; confirm clearance and height.

Review outputs

validation/pcb-draft.svg / pcb-draft.png: combined copper/outline/fab review.
validation/pcb-draft-3d.png: KiCad render of the carrier and available standard component models. ESP32, OLED and RS-232 assembled module models are absent; the render is not an assembled-device or enclosure fit check.
pcb-placement-draft.pdf: 1:1 front placement/pad/outline drawing. Print at 100%, disable fit-to-page, and confirm the outer width is 82 mm before use. It includes only known module outlines; no guessed U1 body or DE-9 envelope.

Validation and limits

Run from the repository root with the system Python containing KiCad bindings:

/usr/bin/python3 -B hardware/PCB/validate_pcb_draft.py
/usr/bin/python3 -B hardware/PCB/validation/pcb-routing-check.py

The first script exports a fresh saved-schematic netlist and checks the actual PCB pad assignments, component linkage, dimensions, layer count, nominal thickness, mounting holes, track/via sizes and KiCad DRC. It never rewrites the PCB or project. It reports the single expected U2 parity warning explicitly, and fails on any other parity issue, DRC violation or unconnected item. Reports are retained in validation/pcb-parity-drc.json and pcb-validation-summary.json.

The second independently checks continuous copper/hole/edge geometry and original placement/net/UUID preservation against the initial unrouted snapshot. It needs locally installed NumPy and Shapely in addition to pcbnew. It is not a substitute for current-schematic net validation and is specific to this initial layout.

Results with KiCad 10.0.6:

0 physical DRC errors/warnings; 0 unconnected items.
All saved-schematic pad nets match the PCB; 1 expected U2 footprint parity warning.
Independent minimum different-net/copper-to-NPTH gap 0.275 mm; minimum copper/NPTH-to-board-edge gap 0.525 mm.
All 9 electrical footprints, 4 board-only mounts, outline and RF area retained.
Startup PROPERTY_ENUM assertions from the local pcbnew binding are still emitted, but the checks complete successfully.

DRC uses the existing default ignored checks: missing_courtyard, track_not_centered_on_via, tuning_profile_track_geometries, footprint_filters_mismatch, footprint_type_mismatch. No new exclusions were added to hide problems. Missing module courtyards therefore remain an explicit manual release gate. The draft rules do not represent a chosen fabricator's complete capability set. No electrical/hardware/fabrication tests were performed.

Regeneration and project settings

Normal use is to edit the native PCB in KiCad, not regenerate it. The optional generate_pcb_draft.py recreates the unrouted initial placement and discards manual PCB work only with explicit --overwrite; it refuses an open-project lock. KiCad's initial SaveBoard populated the previously minimal .kicad_pro with PCB settings and draft clearance/width rules. The schematic was not modified. If the project was already open, reopen it to load the saved PCB settings before review.

route_pcb_draft.py requires NumPy and pcbnew. By default it never saves; replacing existing tracks requires explicit --route --overwrite --replace-routes. Do not run that over manual routing without a backup. It is a bounded initial-draft router, not a general-purpose autorouter. See validation/pcb-routing-summary.md for algorithm limits and commands. These scripts do not need downloaded packages or services in the current environment and create no manufacturing outputs.

Before fabrication: qualify all module pin maps/footprints and connectors, complete assembly courtyards and RF/USB/DE-9 checks, review power/return paths, verify the existing USB power circuit and OLED pull-ups, confirm procurement and case hardware, rerun ERC/DRC, and perform an independent hardware design review.

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