Commander1024
60c1e279d6
Introduce an editable KiCad 10 schematic and routed two-layer 82 × 80 mm layout with local provisional footprints, validation tooling, and component research. Keep the RS-232 male-module mapping and mechanical clearances explicitly provisional pending hardware verification.
95 lines
4.4 KiB
Python
95 lines
4.4 KiB
Python
#!/usr/bin/env python3
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"""Read-only PCB checks and fresh KiCad reports; does not regenerate or save PCB.
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Requires KiCad's pcbnew binding in system Python. The known U2 footprint parity
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warning is reported explicitly, not hidden or added to KiCad's exclusions.
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"""
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import json
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from pathlib import Path
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import subprocess
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import xml.etree.ElementTree as ET
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import pcbnew as p
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ROOT=Path(__file__).resolve().parent
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PCB=ROOT/"serial-carrier.kicad_pcb"
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OUT=ROOT/"validation"
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def run(*args):
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subprocess.run(args,check=True,cwd=ROOT)
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run("kicad-cli","sch","export","netlist","--format","kicadxml","-o",str(OUT/"pcb-source-netlist.xml"),str(ROOT/"serial-carrier.kicad_sch"))
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run("kicad-cli","pcb","drc","--format","json","--all-track-errors","--severity-all","--schematic-parity","-o",str(OUT/"pcb-parity-drc.json"),str(PCB))
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board=p.LoadBoard(str(PCB))
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source=ET.parse(OUT/"pcb-source-netlist.xml").getroot()
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comps={c.get("ref"):c for c in source.findall("components/comp")}
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footprints={f.GetReference():f for f in board.GetFootprints()}
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assert set(footprints)==set(comps)|{"H1","H2","H3","H4"}
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assert board.GetCopperLayerCount()==2
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assert p.ToMM(board.GetDesignSettings().GetBoardThickness())==1.6
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outline=[d for d in board.GetDrawings() if d.GetLayer()==p.Edge_Cuts]
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assert len(outline)==6
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points={(round(p.ToMM(v.x)-100,5),round(p.ToMM(v.y)-100,5)) for d in outline for v in (d.GetStart(),d.GetEnd())}
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assert points=={(0,0),(82,0),(82,80),(36,80),(36,61),(0,61)}
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assert max(x for x,y in points)-min(x for x,y in points)==82
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assert max(y for x,y in points)-min(y for x,y in points)==80
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padnets={}
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for net in source.findall("nets/net"):
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for node in net.findall("node"):
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padnets[(node.get("ref"),node.get("pin"))]=net.get("name")
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seen=set()
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for ref,comp in comps.items():
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fp=footprints[ref]
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assert fp.GetValue()==comp.findtext("value"),ref
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assert fp.GetPath().AsString().endswith("/"+comp.findtext("tstamps")),ref
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wanted=comp.findtext("footprint")
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if ref=="U2":
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assert not wanted
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assert fp.GetFPIDAsString()=="Carrier:MAX3243_Reference_Provisional"
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else:
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assert fp.GetFPIDAsString()==wanted,ref
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for pad in fp.Pads():
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if not pad.GetNumber():
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continue
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key=ref,pad.GetNumber()
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assert pad.GetNetname()==padnets[key],(key,pad.GetNetname(),padnets[key])
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seen.add(key)
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assert seen==set(padnets),"Missing or extra electrical pads"
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for ref in ("H1","H2","H3","H4"):
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assert footprints[ref].IsBoardOnly()
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pads=list(footprints[ref].Pads())
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assert len(pads)==1 and pads[0].GetDrillSize().x==p.FromMM(3.2)
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assert pads[0].GetAttribute()==p.PAD_ATTRIB_NPTH
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tracks=list(board.GetTracks())
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assert tracks,"Draft unexpectedly unrouted"
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for track in tracks:
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if isinstance(track,p.PCB_VIA):
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assert track.GetDrillValue()==p.FromMM(0.3)
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assert track.GetWidth(p.F_Cu)==p.FromMM(0.7)
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else:
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assert track.GetLayer() in (p.F_Cu,p.B_Cu)
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expected=0.5 if track.GetNetname() in ("/+3V3","/GND") else 0.25
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assert track.GetWidth()==p.FromMM(expected)
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report=json.loads((OUT/"pcb-parity-drc.json").read_text())
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assert not report["violations"],report["violations"]
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assert not report["unconnected_items"],report["unconnected_items"]
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parity=report["schematic_parity"]
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assert len(parity)==1 and parity[0]["type"]=="footprint_symbol_mismatch",parity
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assert len(parity[0]["items"])==1 and parity[0]["items"][0]["uuid"]==footprints["U2"].m_Uuid.AsString()
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summary={
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"carrier_bounds_mm":[82,80],
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"copper_layers":2,
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"draft_thickness_mm":1.6,
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"electrical_footprints":len(comps),
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"proposed_M3_mounts":4,
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"physical_DRC_violations":0,
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"unconnected_items":0,
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"schematic_pad_nets_match":True,
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"known_parity_warning":"U2 provisional female-reference footprint assigned on PCB only; schematic footprint intentionally blank",
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"ignored_DRC_checks":report["ignored_checks"],
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"not_validated":["male module pin map/fit", "assembly envelope and heights", "header/socket fit", "RF performance and antenna clearance", "power/return-path integrity", "USB power path", "OLED pull-ups", "fabrication process", "hardware operation"],
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}
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(OUT/"pcb-validation-summary.json").write_text(json.dumps(summary,indent=2)+"\n")
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print("PCB draft verified: 82 x 80 mm; 2 copper layers; 0 physical DRC violations; 0 unrouted.")
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print("All schematic pad nets match. One expected U2 footprint parity warning remains visible.")
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print("Not fabrication-ready; see pcb-draft-notes.md and ignored checks in the DRC report.")
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