Commander1024
60c1e279d6
Introduce an editable KiCad 10 schematic and routed two-layer 82 × 80 mm layout with local provisional footprints, validation tooling, and component research. Keep the RS-232 male-module mapping and mechanical clearances explicitly provisional pending hardware verification.
123 lines
6.0 KiB
Python
123 lines
6.0 KiB
Python
#!/usr/bin/python3
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"""Read-only draft audit; needs pcbnew, numpy, shapely and kicad-cli.
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Writes fresh DRC and audit JSON reports, never modifies the board.
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Independent continuous centreline/radius checks complement KiCad DRC. Restricted
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here to the existing circle/axis-aligned rectangular THT pads and straight tracks.
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"""
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from collections import Counter
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import hashlib
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import importlib.util
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import json
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from pathlib import Path
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import subprocess
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import pcbnew as p
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from shapely.geometry import Point, LineString, Polygon, box
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ROOT = Path(__file__).resolve().parent.parent
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spec = importlib.util.spec_from_file_location('router', ROOT / 'route_pcb_draft.py')
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r = importlib.util.module_from_spec(spec)
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spec.loader.exec_module(r)
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board = p.LoadBoard(str(r.PCB))
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original = p.LoadBoard(str(ROOT / 'validation/pcb-routing-input.kicad_pcb'))
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assert r.identity(board) == r.identity(original), 'immutable source geometry/linkage changed'
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items, holes = [], []
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for f in board.GetFootprints():
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for pad in f.Pads():
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xy = r.pos(pad)
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assert pad.GetOrientationDegrees() % 90 == 0
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assert pad.GetShape() in (p.PAD_SHAPE_CIRCLE, p.PAD_SHAPE_RECT)
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if pad.GetShape() == p.PAD_SHAPE_CIRCLE:
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assert pad.GetSize().x == pad.GetSize().y
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geom, radius = Point(xy), p.ToMM(pad.GetSize().x) / 2
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else:
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bb = pad.GetBoundingBox()
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geom = box(p.ToMM(bb.GetX()), p.ToMM(bb.GetY()),
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p.ToMM(bb.GetRight()), p.ToMM(bb.GetBottom()))
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radius = 0
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label = f.GetReference() + '.' + pad.GetNumber() + ':' + pad.m_Uuid.AsString()
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layers = {l for l in r.LAYERS if pad.IsOnLayer(l)}
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items.append((label, pad.GetNetCode(), layers, geom, radius))
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if pad.GetDrillSize().x:
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assert pad.GetDrillSize().x == pad.GetDrillSize().y
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holes.append((label, Point(xy), p.ToMM(pad.GetDrillSize().x) / 2, False))
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track_lengths = Counter()
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widths = Counter()
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for t in board.GetTracks():
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is_via = isinstance(t, p.PCB_VIA)
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if is_via:
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geom, radius, layers = Point(r.pos(t)), p.ToMM(t.GetWidth(p.F_Cu)) / 2, set(r.LAYERS)
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assert abs(radius - 0.35) < 1e-8 and t.GetDrillValue() == r.mm(0.3)
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holes.append((t.m_Uuid.AsString(), geom, 0.15, True))
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else:
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geom = LineString([(p.ToMM(t.GetStart().x), p.ToMM(t.GetStart().y)),
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(p.ToMM(t.GetEnd().x), p.ToMM(t.GetEnd().y))])
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radius, layers = p.ToMM(t.GetWidth()) / 2, {t.GetLayer()}
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expected = 0.5 if t.GetNetname() in ('/+3V3', '/GND') else 0.25
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assert abs(2 * radius - expected) < 1e-8
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widths[str(2 * radius)] += 1
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track_lengths[t.GetNetname()] += geom.length
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items.append((t.m_Uuid.AsString(), t.GetNetCode(), layers, geom, radius))
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min_clearance = float('inf')
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closest = None
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for i, a in enumerate(items):
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for b in items[i + 1:]:
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if not a[2].intersection(b[2]) or (a[1] and a[1] == b[1]):
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continue
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distance = a[3].distance(b[3]) - a[4] - b[4]
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if distance < min_clearance:
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min_clearance, closest = distance, (a[0], b[0])
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assert min_clearance >= 0.25 - 1e-6, (min_clearance, closest)
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outline = Polygon([(100,100),(182,100),(182,180),(136,180),(136,161),(100,161)])
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rf = box(110, 100, 131, 113)
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min_edge, min_rf = float('inf'), float('inf')
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for label, net, layers, geom, radius in items:
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assert outline.covers(geom), label
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edge_gap = outline.boundary.distance(geom) - radius
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rf_gap = rf.distance(geom) - radius
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min_edge, min_rf = min(min_edge, edge_gap), min(min_rf, rf_gap)
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assert edge_gap >= 0.5 - 1e-6, (label, edge_gap)
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assert rf_gap > 0, (label, rf_gap)
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min_via_hole_gap = float('inf')
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for i, a in enumerate(holes):
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for b in holes[i + 1:]:
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if not (a[3] or b[3]):
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continue
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gap = a[1].distance(b[1]) - a[2] - b[2]
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min_via_hole_gap = min(min_via_hole_gap, gap)
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assert gap >= 0.25 - 1e-6, (a[0], b[0], gap)
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# Refusal paths must leave the routed board byte-for-byte unchanged.
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before = r.PCB.read_bytes()
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guards = []
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for args in (['--route'], ['--route', '--overwrite'], []):
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result = subprocess.run(['/usr/bin/python3', '-B', str(ROOT/'route_pcb_draft.py'), *args],
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capture_output=True, text=True, timeout=20)
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assert result.returncode == 2, (args, result.stdout, result.stderr)
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assert r.PCB.read_bytes() == before
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guards.append({'args': args, 'exit_code': result.returncode,
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'reason': result.stderr.splitlines()[-1]})
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subprocess.run(['kicad-cli', 'pcb', 'drc', '--format', 'json', '--all-track-errors',
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'--severity-all', '--exit-code-violations', '-o',
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str(ROOT/'validation/pcb-routing-drc.json'), str(r.PCB)],
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check=True, timeout=60)
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assert r.PCB.read_bytes() == before, 'board changed during audit'
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drc = json.loads(ROOT.joinpath('validation/pcb-routing-drc.json').read_text())
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assert not drc['violations'] and not drc['unconnected_items']
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report = dict(immutable_geometry_nets_pads_linkage_preserved=True,
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board_sha256=hashlib.sha256(before).hexdigest(),
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independent_min_different_net_or_npth_clearance_mm=min_clearance,
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closest_items=closest, min_copper_or_npth_edge_gap_mm=min_edge,
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min_rf_gap_mm=min_rf, min_via_to_other_drilled_hole_gap_mm=min_via_hole_gap,
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track_width_counts=widths, routed_length_mm_by_net=track_lengths,
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tracks=sum(not isinstance(t,p.PCB_VIA) for t in board.GetTracks()),
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vias=sum(isinstance(t,p.PCB_VIA) for t in board.GetTracks()),
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copper_zones=sum(not z.GetIsRuleArea() for z in board.Zones()),
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drc_freshly_run=True,
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drc_violations=len(drc['violations']), unconnected_items=len(drc['unconnected_items']),
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drc_ignored_checks=drc['ignored_checks'], overwrite_guard_tests=guards)
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ROOT.joinpath('validation/pcb-routing-check.json').write_text(json.dumps(report, indent=2)+'\n')
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print(json.dumps(report, indent=2))
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