Add KiCad module carrier PCB draft
Introduce an editable KiCad 10 schematic and routed two-layer 82 × 80 mm layout with local provisional footprints, validation tooling, and component research. Keep the RS-232 male-module mapping and mechanical clearances explicitly provisional pending hardware verification.
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# Two-layer draft routing result
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Date: 2026-09-20. KiCad 10.0.6; system `/usr/bin/python3`.
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## Saved result
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Actual copper routing is saved in `../serial-carrier.kicad_pcb`, not just a preview
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or an exported proposal. **38/38 required spanning-tree connections across 17
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multi-pad nets routed; KiCad reports 0 unconnected items, 0 errors, 0 warnings.**
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Intentional single-pad `unconnected-(...)` nets retain their original names and
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are not connected to anything else.
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- Two copper layers, F.Cu and B.Cu.
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- 569 straight track segments: 425 at 0.25 mm for signals and 144 at 0.5 mm for
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+3V3/GND. No narrow power-track fallback was necessary.
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- 20 through vias, 0.7 mm copper diameter / 0.3 mm drill.
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- No copper pours: all ground connections were routed explicitly.
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- Original RF rule area, x110..131 / y100..113 mm on both copper layers, preserved.
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No tracks, vias or fills enter the reservation. Minimum copper-to-reservation
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gap measured independently is 0.025 mm; this is geometric compliance with the
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specified provisional boundary, **not validation of an antenna's RF needs**.
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- All 9 electrical footprints and 4 standalone mounting footprints preserved.
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Pad positions, shapes, sizes, drills, types, nets, functions, pin types and UUIDs;
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footprint placement, orientation, library IDs, values, UUIDs and schematic UUID
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paths; net table, outline and RF rule-area geometry/flags match the input.
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- Generator, README, schematic, project and libraries were not edited by routing.
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No external network dependency or manufacturing exports were used.
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## Validation performed
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From `hardware/PCB`:
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```sh
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kicad-cli pcb drc --format json --refill-zones --save-board -o validation/pcb-routing-drc.json serial-carrier.kicad_pcb
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kicad-cli pcb drc --format json --all-track-errors --severity-all --exit-code-violations -o validation/pcb-routing-all-drc.json serial-carrier.kicad_pcb
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/usr/bin/python3 -B validation/pcb-routing-check.py
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```
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Both DRC runs: **0 violations and 0 unconnected items**. No DRC settings or
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exclusions were added or changed. Existing project rules specify 0.25 mm minimum
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clearance, 0.5 mm copper-edge clearance, 0.25 mm minimum track width and 0.7 mm
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minimum via diameter.
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Independent continuous-geometry audit (`pcb-routing-check.json`):
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| Check | Measured minimum | Requirement |
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|---|---:|---:|
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| Different-net copper / copper-to-NPTH clearance | 0.275 mm | 0.25 mm |
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| Copper or NPTH edge to board edge | 0.525 mm | 0.5 mm |
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| Copper / NPTH edge to RF reserve | 0.025 mm | No intersection |
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| Via drill edge to another drilled hole edge | 0.840175 mm | 0.25 mm |
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The audit uses exact straight-line/point/rectangle distance calculations with
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copper radii, rather than the router's raster masks. It also verifies dimensions,
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source-preservation invariants, and three overwrite-refusal cases. Requires
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locally installed `pcbnew`, NumPy and Shapely; the router itself only needs
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`pcbnew` and NumPy.
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DRC still honors the project's pre-existing ignored checks:
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`missing_courtyard`, `track_not_centered_on_via`,
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`tuning_profile_track_geometries`, `footprint_filters_mismatch`, and
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`footprint_type_mismatch`. `--severity-all` does not enable ignored checks.
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The routing subtask compared electrical UUID linkage and pad-net assignments
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with the input board. Subsequent integration also ran fresh schematic-parity DRC
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and added missing symbol metadata fields to the PCB without changing copper.
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That check reports exactly one expected U2 footprint warning (provisional PCB
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footprint versus intentionally blank schematic assignment); no net mismatch.
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See `pcb-parity-drc.json` and `pcb-validation-summary.json`.
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## Method and bounded passes
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`../route_pcb_draft.py` uses a two-layer 8-direction raster A* search, an explicit
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via cost, exact-pad-centre terminal stubs, conservative foreign-copper and hole
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obstacles, and only collinear path compression. It preserves the L-shaped edge
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and RF reservation. Per-net minimum spanning trees connect every physical pad,
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including duplicate switch contacts; short links precede longer links and GND is
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last. It does not optimize return-current paths, topology or total via count.
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1. Initial 0.1 mm raster / 0.04 mm safety margin / 250,000 expansions per search:
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29/38 connections; DRC 0 violations, 9 unconnected.
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2. Increased search allowance to 1,200,000 expansions: 30/38; DRC 0 violations,
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8 unconnected. Some raster header passages were blocked, not just expensive.
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3. Final 0.05 mm raster / 0.02 mm additional safety margin, with 0.25 mm physical
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clearance unchanged: 38/38 in approximately 26.5 seconds; DRC fully connected.
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Each pass had a 240-second routing deadline. No unresolved routing remains.
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A KiCad Python binding ownership problem in the first replacement attempt caused
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an exception/segfault before any board save. Replacement now uses `board.Delete`
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instead of `board.Remove`; the subsequent save and no-save rerun both passed.
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The known startup PROPERTY_ENUM assertions do not prevent validation.
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## Rerun safety
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By default the script never saves. The existing routed board is protected even
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from a preview unless `--replace-routes` is given. A preview can be run with:
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```sh
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/usr/bin/python3 -B route_pcb_draft.py --replace-routes --seconds 240
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```
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This exact no-save workflow was tested: it again found 38/38 connections, 569
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segments and 20 vias, and left the board byte-for-byte unchanged.
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**The following command discards all existing/manual tracks and vias**, then
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replaces them with fresh draft routing. Back up manual work first:
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```sh
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/usr/bin/python3 -B route_pcb_draft.py --route --overwrite --replace-routes --seconds 240 --max-expansions 1200000
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```
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The script refuses a PCB-editor lock, unexpected outline/RF/board structure,
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unsupported pad orientation/layers, unapproved existing routes, or detected board
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changes before save. Candidate serialization must preserve immutable geometry
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and linkage before replacing the board. It deliberately does not run DRC itself:
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rerun the validation commands after any routing change. Runtime/expansion limits
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can produce a partial board; inspect both the run report and actual DRC, not just
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the script exit status.
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## Evidence and remaining limitations
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- `pcb-routing-input.kicad_pcb`: unrouted input snapshot, after baseline DRC save.
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- `pcb-routing-baseline.json`: 38 unconnected / no violations before routing.
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- `pcb-routing-pass1-drc.json`, `pcb-routing-pass2-drc.json`: intermediate DRC.
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- `pcb-routing-pass2.log`, `pcb-routing-pass3.log`: bounded routing progress.
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- `pcb-routing-run.json`: final saved-route metrics and connection list.
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- `pcb-routing-drc.json`, `pcb-routing-all-drc.json`: final KiCad DRC evidence.
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- `pcb-routing-check.py`, `pcb-routing-check.json`: repeatable independent audit.
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- `pcb-routing-dry-run.log`: successful final no-save reproduction.
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Routing-only DRC-saved snapshot SHA-256 (before integration copied schematic
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metadata fields): `bf94b6c9b00c43a97f933054758a2c9d6541981ae09f2f285dcdb567bd73d9b1`.
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The current post-integration hash is recorded by `pcb-routing-check.json`;
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geometry, pad-net linkage and copper are unchanged by the metadata copy.
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**Still DRAFT / NOT FOR FABRICATION.** Provisional module/connector geometry,
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antenna envelope, assembly/courtyard clearances, USB access, male RS-232 connector
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fit, physical pin mapping, power integrity, EMI and hardware operation are not
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qualified by routing or DRC. All previously documented mechanical/electrical
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release gates remain. No physical-device or manufacturing validation performed.
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