Commander1024
60c1e279d6
Introduce an editable KiCad 10 schematic and routed two-layer 82 × 80 mm layout with local provisional footprints, validation tooling, and component research. Keep the RS-232 male-module mapping and mechanical clearances explicitly provisional pending hardware verification.
106 lines
5.7 KiB
Markdown
106 lines
5.7 KiB
Markdown
# Provisional carrier module footprints
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These project-local footprints are in `Carrier.pretty`. They are mechanical
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starting points, **not fabrication-ready connector selections**. Both are now
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assigned to their matching symbols in the native schematic through the project
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library tables and used in the routed PCB draft. The assembled module 3D models
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are not provided. See `pcb-draft-notes.md` for placement/routing and
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`rs232-footprint-notes.md` for the additional provisional RS-232 reference footprint.
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## Shared pad/drill provenance and limits
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Reference inspected locally: installed KiCad library footprint
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`Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical`, file
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`/usr/share/kicad/footprints/Connector_PinHeader_2.54mm.pretty/PinHeader_1x04_P2.54mm_Vertical.kicad_mod`
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(format version `20260206`; local KiCad `10.0.6-1.fc44`).
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Both footprints use that reference's **1.70 × 1.70 mm plated through-hole pads,
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1.00 mm drills, rectangular pad 1, and circular remaining pads**, on
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`*.Cu` and `*.Mask`, with unused copper layers retained. Nominal pitch is 2.54 mm.
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Only the reference's pad/drill convention is reused, not its connector body,
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courtyard, or 3D model. HW678 pad 23 is circular: only overall pad 1 is rectangular.
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**PROVISIONAL connector fit — awaiting the selected actual pin/socket datasheet.**
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Breadboard fit supports centre spacing, not drill size, finished-hole tolerance,
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annular-ring suitability, socket body clearance, mating height, or solderability.
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Validate those against the actual final headers and beta-test sockets and the PCB
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fabricator's process before release. No electrical nets or ESP32 GPIO assignments
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are inferred. No courtyards are supplied: module/connector assembly clearances
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remain incomplete, so automated courtyard checks cannot establish fit.
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Coordinates below are millimetres, unrotated on the carrier front side, X right
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and Y down. Views are not mirrored. Placement on the back side or viewing the
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module from its solder side requires the appropriate KiCad transform; do not
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silently reverse the numbering.
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## `Carrier:OLED_26mm_I2C_Provisional`
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Origin: top-left corner of the module PCB, viewed from the front/display side,
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header at the top. User-verified geometry from the current request and the later
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mechanical-evidence section of `README.md`:
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| Pad | Signal | X | Y |
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|---|---|---:|---:|
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| 1 | GND | 9.19 | 1.50 |
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| 2 | VCC | 11.73 | 1.50 |
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| 3 | SCL | 14.27 | 1.50 |
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| 4 | SDA | 16.81 | 1.50 |
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- PCB boundary: (0, 0) to (26, 26), solid rectangle on `F.Fab`.
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This depicts the module, not the carrier's routed edge; no `Edge.Cuts` is used.
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- Four unnumbered, non-plated through holes, diameter 2.00 mm, at
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(1.75, 1.75), (24.25, 1.75), (1.75, 24.25), (24.25, 24.25).
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Hole centres are 1.75 mm from adjacent edges, with 22.50 mm spacing in both axes.
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These transfer the verified module hole geometry to the carrier; they do not
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select screws, inserts, bosses, or hardware clearance envelopes.
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- Display boundary: (1, 4.5) to (25.5, 21), 24.5 × 16.5 mm, dashed on `F.Fab`.
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This is the supplied display boundary, not a verified active-pixel area or case cutout.
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- Pad-to-signal mapping is documented here and in the footprint description;
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footprint pads themselves have numbers, not assigned nets.
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The approved geometry supersedes the earlier 22.16 mm hole-spacing measurement:
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22.50 mm hole spacing, Y=1.50 mm header centres, and the centred header coordinates
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above apply. See README for the user-reported successful template fit check.
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## `Carrier:HW678_2x22_Provisional`
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Component/top view: antenna up, USB connectors down. Origin is the top-left header
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centre (pad 1), **not a PCB corner**.
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- Left row: pads 1 through 22, top to bottom, X=0.
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- Right row: pads 23 through 44, top to bottom, X=25.40.
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- Y=0 through 53.34 in 2.54 mm increments for each row (21 intervals).
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- User breadboard fit verifies nominal 2.54 mm pitch and 25.40 mm row spacing;
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these supersede the earlier raw caliper dimensions in README.
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- Numbering follows the project's explicit convention, not a generic dual-row
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connector's alternating or counterclockwise numbering. Physical numbers do
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**not** establish GPIO, supply, or ground assignments.
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- Only pads and annotation text are present. **No PCB outline, antenna keepout,
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courtyard, USB envelope, mounting holes, or 3D model is guessed.** Text positions
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are annotations, not dimensional evidence. Outline registration, antenna extent,
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connector offsets/overhang, and assembly height remain unknown.
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## Validation and release gates
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Validation performed with KiCad 10.0.6 `pcbnew.FootprintLoad`: both footprints
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parsed successfully. Assertions passed for pad counts, all numbered pad positions,
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pad shapes/types/sizes/drills, OLED NPTH positions and diameters, both OLED `F.Fab`
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rectangle bounds, and absence of courtyards, `Edge.Cuts`, and keepout zones.
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HW678 was also checked to contain no graphical shapes. The local Python binding
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emitted three startup `PROPERTY_ENUM` assertions (also seen on a version-only
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import); these did not prevent loading or the checks from passing.
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Repeat the retained footprint regression checks from the repository root with:
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```sh
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/usr/bin/python3 -B hardware/PCB/validate_footprints.py
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```
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This requires the system Python with KiCad's `pcbnew` binding. It checks the
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native-loaded pad counts, coordinates, pad types, sizes, drills and geometry. Parsing is
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not DRC, electrical verification, connector fit verification, or fabrication approval.
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Print both footprints at 1:1 and check the real assemblies, especially HW678 row
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numbering/orientation. Before layout release, select and verify connectors, map
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HW678 pins from reliable board evidence, and establish module envelopes,
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antenna restrictions, USB access, mounting hardware, and courtyards.
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