Commander1024
60c1e279d6
Introduce an editable KiCad 10 schematic and routed two-layer 82 × 80 mm layout with local provisional footprints, validation tooling, and component research. Keep the RS-232 male-module mapping and mechanical clearances explicitly provisional pending hardware verification.
118 lines
6.4 KiB
Markdown
118 lines
6.4 KiB
Markdown
# MAX3243 carrier — PROVISIONAL female CAD reference / VERIFY MALE
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Footprint: `Carrier:MAX3243_Reference_Provisional` in
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`Carrier.pretty/MAX3243_Reference_Provisional.kicad_mod`.
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Intended only for a <=100 × 100 mm, two-copper-layer carrier PCB draft.
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No schematic assignment or edits are made. This footprint does not establish
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whole-board fit, connector access, DRC compliance, or fabrication readiness.
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## Evidence and scope
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The user reports that the male **6253** module has the same dimensions. This is
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not confirmation of its pad map. Geometry below is taken from published **female
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5988** Eagle CAD, not verified male-specific CAD. Confirm the purchased module's
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identity, orientation, header numbering, outline and mounting geometry before
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release. Never infer header order from DE-9 gender or mating-face numbering.
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Source: [Adafruit PCB repository](https://github.com/adafruit/Adafruit-RS-232-Level-Shifter-Breakout-PCB),
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commit `63c6200bb3ef17d491089cfa6441b1810d79bb20`.
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Local original: `reference/Adafruit RS-232 Full Pinout Level-Shifter Breakout.brd`;
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SHA-256 `6a7b35ef909f5a2d243c326c34db3957aaa01275bf2aac8e0c749ff18162e870`
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was rechecked against the file. See `adafruit-research.md` for provenance and
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female/male distinctions.
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CAD-derived geometry adapted from the design by **Limor Fried/Ladyada for Adafruit
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Industries**, under **CC BY-SA 3.0 Unported**:
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https://creativecommons.org/licenses/by-sa/3.0/ . The CAD-derived footprint and
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these CAD-derived notes use that license. Preserve the full upstream notices in
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`reference/README.md` and `reference/license.txt` when redistributing this adaptation.
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Changes: coordinate transformation, carrier pad convention, NPTH carrier holes,
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and provisional annotations; no module circuitry or connector package copied.
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## View, origin and exact nominal geometry
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Front/component top view, module facing up, DE-9 toward the top (**negative Y**).
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Origin is header JP2 pin 1, not a PCB corner. X increases rightward; Y downward.
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Transform Eagle board coordinates in mm with:
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`x = X - 1.905; y = 2.667 - Y`.
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- Pads 1…12: `(2.54 × (N - 1), 0)`, first-to-last span 27.94 mm.
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- Full bare-module outline is on `F.Fab`, **not carrier `Edge.Cuts`**.
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Bounds: X = -1.905…29.845, Y = -26.670…2.667 (31.750 × 29.337 mm).
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Top corners are square. Bottom corners retain the source 2.540 mm radius arcs.
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- Left arc: (-1.905, 0.127) to (0.635, 2.667), centre (0.635, 0.127).
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Right arc: (27.305, 2.667) to (29.845, 0.127), centre (27.305, 0.127).
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Midpoints use radius/sqrt(2), rounded to nine decimal places in the file;
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the arcs are not chamfers or a bounding-box approximation.
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- Two unnumbered **3.00 mm NPTH carrier holes**: (1.905, -8.763) and
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(26.035, -8.763), spacing 24.130 mm. These transfer module-hole centres and
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drill diameter only. The source module holes are actually plated, 3.60 mm
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copper / 3.00 mm drill, unconnected in the source signal map. Carrier NPTH
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deliberately does not copy that plating or assign electrical connections.
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No screw, washer, standoff or tool-access clearance is implied.
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## Provisional carrier pads and female reference map
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Same convention documented in `footprint-notes.md` for the other carrier modules:
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**1.70 × 1.70 mm PTH pads / 1.00 mm drills**, rectangular pad 1, circular pads
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2…12, `*.Cu` and `*.Mask`, unused copper layers retained. That convention derives
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from the installed KiCad `PinHeader_1x04_P2.54mm_Vertical`; it is not a selected
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header/socket qualification. The source module itself uses 1.9304 mm round pads.
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Confirm actual pins/sockets, finished-hole tolerances, annular rings and assembly
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height before fabrication. Square pad 1 is a carrier marker, not source evidence.
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| Pad | X (mm), Y=0 | Female label | Female CAD net |
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|---:|---:|---|---|
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| 1 | 0.00 | Vin | VCC |
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| 2 | 2.54 | GND | GND |
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| 3 | 5.08 | DCD | DCD |
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| 4 | 7.62 | RX | RXD |
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| 5 | 10.16 | TX | TXD |
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| 6 | 12.70 | DTR | DTR |
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| 7 | 15.24 | DSR | DSR |
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| 8 | 17.78 | RTS | RTS |
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| 9 | 20.32 | CTS | CTS |
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| 10 | 22.86 | RI | RI |
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| 11 | 25.40 | VLD | !INVALID |
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| 12 | 27.94 | OFF | !FORCEOFF |
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**This is the female reference map, NOT a confirmed male map.** Footprint pads
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have numbers only, no assigned nets. OFF is active low; VLD indicates valid input
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when high. This project's logic interface requires 3.3 V Vin.
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## Intentionally omitted / release gates
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**No verified DE-9 mechanical envelope is available, so none is drawn.** No
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male overhang, shell, mating plug, cable bend, enclosure cutout, height, underside
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keepout, mounting-hardware clearance, 3D model or courtyard is invented. Female
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library silkscreen and product bounding dimensions are not male clearance data.
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The F.Fab outline describes only the bare module PCB, not the assembled envelope.
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There is **no fake courtyard**; courtyard checks cannot establish assembly fit.
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Short silkscreen labels identify PROVISIONAL / FEMALE CAD REF / VERIFY MALE.
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Before layout release: verify male pad map and orientation against the actual
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module or authoritative male CAD; perform a 1:1 fit check; select headers and
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mounting hardware; verify assembled and mating envelopes; then establish real
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clearances/courtyard and check the complete <=100 × 100 mm two-layer layout.
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## Validation performed
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KiCad **10.0.6** `pcbnew.FootprintLoad` successfully loaded the footprint using
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system Python (`/usr/bin/python3 -B`) in a read-only inline check. Assertions passed
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for all 12 numbered pad positions against source JP2 package/element coordinates,
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female signal-contactref order, pad sizes/drills/shapes and copper/mask presence,
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no assigned header nets, both NPTH centres/sizes/drills, and all six transformed
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source outline segments including both 90-degree, 2.540 mm radius arcs and centres.
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Also checked absence of courtyard, Edge.Cuts, zones and 3D models.
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The first check assumed arc endpoint order was preserved; KiCad normalizes arc
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orientation. The corrected check matches endpoint pairs independent of order and
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verifies radius, angle and centre; it passed without changing geometry. The
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binding emitted the same three startup `PROPERTY_ENUM` assertions documented for
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other module validation; these did not prevent loading or successful checks.
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No hardware fit test, male electrical verification, board DRC or firmware build
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was performed. Existing `validate_footprints.py` was not changed and does not
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cover this new footprint. Only this notes file and the new footprint were written;
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schematic, project and lock files were left untouched.
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